DSP56857 datasheet(261/662 Pages) FREESCALE

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SCI Register Descriptions (SCI0_BASE = $1FFFE0 and SCI1_BASE = $1FFDF8)

Serial Communications Interface (SCI), Rev. 4

Freescale Semiconductor

10-25

10.9.2.5 Wake Up Condition (WAKE)—Bit 11

This bit determines which condition wakes up the SCI: a Logic 1 (address mark) in the

MSB position of a received data character or an idle condition on the RXD pin.

•

0 = Idle line wake up

•

1 = Address mark wake up

10.9.2.6 Polarity (POL)—Bit 10

This bit determines whether to invert the data as it goes from the transmitter to the TXD

pin and from the RXD pin to the receiver. All bits, Start, Data, and Stop, will be inverted

as they leave the Transmit Shift Register and before they enter the Receive Shift register.

•

0 = Doesn’t invert Transmit and Receive Data bits (Normal mode)

•

1 = Invert Transmit and Receive Data bits (Inverted mode)

Note:

It is recommended the POL bit be toggled only when both TE and RE = 0.

10.9.2.7 Parity Enable (PE)—Bit 9

This bit enables the parity function. When enabled, the parity function replaces the MSB

of the data character with a parity bit.

•

0 = Parity function disabled

•

1 = Parity function enabled

10.9.2.8 Parity Type (PT)—Bit 8

This bit determines whether the SCI generates and checks for even parity or odd parity of

the data bits. With even parity, an even number of ones, clears the parity bit. An odd

number of ones sets the parity bit. With odd parity, an odd number of ones, clears the

parity bit and an even number of ones sets the parity bit.

•

0 = Even parity

•

1 = Odd parity

10.9.2.9 Transmitter Empty Interrupt Enable (TEIE)—Bit 7

This bit enables the Transmit Data Register Empty (TDRE) flag to generate interrupt

requests.

•

0 = TDRE interrupt requests disabled

•

1 = TDRE interrupt requests enabled

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