DSP56857 datasheet(93/662 Pages) FREESCALE

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Program Boot ROM

Overview, Rev. 4

Freescale Semiconductor

3-5

3.2.3 Boot Mode 2: Normal Expanded Mode

The PRAM DISABLE remains at zero, leaving both internal program and data RAM enabled. No

code is loaded. The bootstrap program simply vectors to external program memory location

P:$040000 using CS0 as the chip select.

3.2.4 Boot Mode 3: Development Expanded Mode

The PRAM DISABLE remains at one, leaving internal data RAM enabled, but the internal

program RAM is disabled. All references to internal program memory space are subsequently

directed to external program memory. No code is loaded. The bootstrap program simply vectors

to program memory location P:$000000 using CS0 as the chip select.

3.2.5 Boot Mode 4: Bootstrap From Host Port–Single Strobe Clocking

The PRAM DISABLE remains at zero, leaving both internal program and data RAM enabled.

The bootstrap program configures the Host Port for single strobe access, loading program

memory from the Host Port before jumping to the start of the user code.

3.2.6 Boot Mode 5: Bootstrap From Host Port–Dual Strobe Clocking

The PRAM DISABLE remains at zero, leaving both internal program and data RAM enabled.

The bootstrap program configures the Host Port for dual strobe access, loading program memory

from the Host Port before jumping tot he start of the user code.

3.2.7 Boot Mode 6: Bootstrap From SCI

The PRAM DISABLE remains at zero, leaving both internal program and data RAM enabled. It

configures the SCI for 38400 baud transfers with a 4MHz or 19200 with 2MHz crystals. It also

enables the PLL to operate during the boot process. The bootstrap program then loads program

memory from the SCI port and jumps to the start of the user code. External clocking must be

between 2MHz and 4MHz. It uses the PLL but leaves it off when complete. The data format is:

•

One Start Bit

•

Eight-Data Bits

•

No Parity Bit

•

One Stop Bit

•

Flow Control Off

3.2.8 Boot Mode 7: Reserved for Future Use

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