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DSP56857 bảng dữ liệu(PDF) 55 Page - Freescale Semiconductor, Inc |
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DSP56857 bảng dữ liệu(HTML) 55 Page - Freescale Semiconductor, Inc |
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55 / 662 page ![]() System Bus Controller 5685X Overview, Rev. 4 Freescale Semiconductor 1-23 • Enhanced Synchronous Serial Interface (ESSI) module • Serial Peripheral Interface (SPI) module • Programmable General-Purpose I/O (GPIO) module • Eight-bit Parallel Host Interface (HI8) 1.5 System Bus Controller The System Bus Controller (SBC) controls a number of functions essential to the transfer of data between the core, DMA controllers and memory within the 56853/854/855/857/858 systems. 1.5.1 Operation The SBC performs a number of central roles in the transfer of data between either the core or DMA controller and memory space. In every clock cycle, the SBC determines whether the core or DMA is bus master, which memory device in any space is active, and if the core clock is active. Through these actions, all data transfers are completed at maximum bus efficiency. The SBC is capable of supporting one core and one DMA controller of up to six channels (operating in X1 data space only): • Up to three program memory address spaces • Up to two X1 memory address spaces • Single X2 memory address space Either the core or DMA controller are capable of initiating memory transfers. Bus mastership is arbitrated by the SBC, and the device which is permitted to access the bus on any given cycle is referred to as the active bus master. 1.5.2 IPBus Bridge (IPBB) The IPBus Bridge (IPPB) provides a means for communication between the high speed core and the low-bandwidth devices on the IP peripheral bus. Among other functions, the bridge is responsible for maintaining an orderly and synchronized communication between devices on both sides running at two different clock frequencies. Figure 1-8 denotes the position and interface of the IPBus Bridge with other main blocks within the chip. Other connections in the figure not pertaining to the primary function of the bridge are omitted for clarity; nevertheless, they will be discussed as appropriate. A brief description of bridge’s interface with various main components on both sides is also provided. |
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