DSP56857 datasheet(97/662 Pages) FREESCALE

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Memory Maps

Overview, Rev. 4

Freescale Semiconductor

3-9

Note:

The X (data) address space for all parts is actually 24 bits ($000000 - $FFFFFF) but

only 21 bits are brought out externally. The chip selects can be programmed to allow

data accesses above $1FFFFF. In this case the data space can be thought of as multiple

2M word pages.

3.3.1 Memory Register Summary

This summary lists all accessible EOnCE Memory mapped registers in the 5685x devices, in

Table 3-1. The Peripheral System Configurations are listed in Table 3-15.

3.3.1.1 Memory Mapped Registers

Table 3-1 lists all of the EOnCE Memory mapped registers in the 5685x devices. Please consult

the DSP56800E Reference Manual (DSP56800ERM) for complete details of the following table.

Table 3-1. EOnCE Memory Map (EOnCE_BASE = $FFFF00)

Address Offset

Base + $FF

OTX1/ORX1

Transmit Register Upper Word

Receive Register Upper Word

Base + $FE

OTX/ORX

Transmit Register

Receive Register

Base + $FD

OTXRXSR

Transmit /Receive Status/ Control Reg.

Base + $FC

OCLSR

Core Lock/Unlock Status Register

Reserved

Base + $A0

OCR

Control Register

Base + $9F

—

Instruction Step Counter

Base + $9E

OSCNTR

Instruction Step Counter

Base + $9D

OSR

Status Register

Base + $9C

OBASE

Peripheral Base Address Register

Base + $9B

OTBCR

Trace Buffer Control Register

Base + $9A

OTBPR

Trace Buffer Pointer Register

Base + $99

—

Trace Buffer Register Stages

Base + $98

OTB

Trace Buffer Register Stages

Base + $97

—

Breakpoint Unit [0] Control Register

Base + $96

OBCR

Breakpoint Unit [0] Control Register

Base + $95

—

Breakpoint 1 Unit [0] Address Register

Base + $94

OBAR1

Breakpoint 1 Unit [0] Address Register

Base + $93

—

Breakpoint 2 Unit [0] Address Register

Base + $92

OBAR2

Breakpoint 2 Unit [0] Address Register

Base + $91

—

Breakpoint 1 Unit [0] Mask Register

Base + $90

OBMSK

Breakpoint 1 Unit [0] Mask Register

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