DSP56857 datasheet(78/662 Pages) FREESCALE

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Signal and Package Information

5685X Digital Signal Controller User Manual, Rev. 4

2-10

Freescale Semiconductor

2.2 Signal and Package Information

All digital inputs have a weak internal pull-up circuit associated with them. These pull-up

circuits are enabled by default. Exceptions:

1. When a pin has GPIO functionality, the pull-up may be disabled under

software control

2. Mode pins D13, D14, and D15 have no pull-up

3. TCK has a weak pull-down circuit always active

4. Bidirectional I/O pull ups automatically disabled when the output is enabled

The following tables are presented consistently with the Signals Identified by Functional

Group figure.

1. BOLD entries in the Type column represents the state of the pin just out of

reset.

2. Output(Z) means an output is in a High-Z condition.

2.3 Power, Ground and Peripheral Signals

The following tables illustrate power, ground, and bypass capacitor pinout data. Table 2-2

through Table 2-9 displays the physical layout of various grounds and voltage input

signals associated with the input/output ring. Signal names in parentheses on the same

table row provide the GPIO alternative pin function.

Table 2-2. Power Inputs

Signal Name

Signal Description

853

Pins

854

Pins

855

Pins

857

Pins

858

Pins

VDD

Power—These pins provide power to the internal structures of the

chip. They all should be attached to VDD.

VDDIO

Power—These pins provide power for all I/O and ESD structures of

the chip. They all should be attached to VDDIO (3.3V).

VDDA

Analog Power—These pins supply analog power.

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