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DSP56857 bảng dữ liệu(PDF) 56 Page - Freescale Semiconductor, Inc |
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DSP56857 bảng dữ liệu(HTML) 56 Page - Freescale Semiconductor, Inc |
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56 / 662 page ![]() System Bus Controller 5685X Digital Signal Controller User Manual, Rev. 4 1-24 Freescale Semiconductor 1.5.2.1 System Side Operation On the system side, the IPBus Bridge operates at core frequency and fully supports pipelined communication with the core. The bridge acts as a slave device on this bus. The bridge is responsible for initiating IPBus transactions only per requests initiated by the core, or other system bus masters. Figure 1-8. IPBus Bridge Interface With Other Main Components System Side Operation 1.5.2.2 Peripheral Side Operation On the peripheral side, the IPBus Bridge accesses various devices through a standard non-pipelined IPBus interface. Separate bus lines are used for read and write transactions. The IPBus Bridge also interfaces with an External Memory Interface (EMI) block. The IPBus operates at half of the core frequency. IP IP X1 DATA 56800E CORE 416 21 XAB1 CDBR CDBW X2 DATA RAM 1-1/2 PORT XAB2 XDB2 PROGRAM RAM PAB PDB 16 21 24 32 IPB_RDATA IPB_WDATA IPB_ADDR RAM IP IPB_R/W IP 16 32 24 EMI INTERFACE CS AD IPBus BRIDGE RD WR |
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