DSP56857 datasheet(60/662 Pages) FREESCALE

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56858 Peripheral Blocks

5685X Digital Signal Controller User Manual, Rev. 4

1-28

Freescale Semiconductor

1.11 56858 Peripheral Blocks

The 56858 provides these peripheral blocks:

•

Two Serial Communication Interfaces (SCI), each with two pins, or four additional GPIO

lines

•

Two Enhanced Synchronous Serial Interfaces (ESSI0 and ESSI1), each with six pins, or

12 additional GPIO lines

•

General Purpose 16-bit Quad Timer (TMR) with four pins or additional GPIO lines

•

Serial Port Interface (SPI) with four pins or additional GPIO lines

•

Eight-bit Parallel Host Interface (HI8) with 16 pins, or 16 additional GPIO lines

•

Interrupt Controller

•

Computer Operating Properly (COP)/Watchdog Timer

•

Time of Day (TOD)

•

Clock Generator

•

System Integration Module (SIM)

•

External Memory Interface (EMI)

•

JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging

1.12 Peripheral Descriptions

The IPBus bridge converts program and data memory accesses to the IPBus-compliant interface

for peripherals and external EMI. This IPBus bridge allows for communication between the core

and peripherals utilizing the CDBR for data and XAB for addresses. To access program space

through the EMI, use PAB and PDB buses. Peripherals run off the IPBus clock at up to 60MHz.

The IPBus clock frequency is half of the system clock frequency.

1.12.1 External Memory Interface

The EMI design includes these distinctive features:

•

Programmable wait states for slower memories (up to 16 IP_CLK access time)

•

Contains four programmable chip selects

•

No external glue logic required for typical systems, if the chip selects are used

•

Chip selects may be independently programmed with various features

•

Program or data space selection

•

Programmable byte enables, to support 8-bit wide external memories

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