DSP56857 datasheet(264/662 Pages) FREESCALE

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SCI Register Descriptions (SCI0_BASE = $1FFFE0 and SCI1_BASE = $1FFDF8)

5685X Digital Signal Controller User Manual, Rev. 4

10-28

Freescale Semiconductor

10.9.3.4 Receiver DMA Enable (RDE)—Bit 0

RDE enables DMA mode transfer of data to the SCIDR. For receive DMA operation, this bit

must be set and a DMA channel must be configured to utilized the request.

•

0 = Receive DMA disabled

•

1 = Receive DMA enabled

10.9.4 SCI Status Register (SCISR)

This register can be read at anytime; however, it cannot be modified by writing. Writes clear

flags.

Figure 10-20. SCI Status Register (SCISR)

See Programmer’s Sheets on Appendix page B-58

10.9.4.1

Transmit Data Register Empty Flag (TDRE)—Bit 15

This bit is set when the Transmit Shift register receives a character from the SCI Data Register

(SCIDR). Clear TDRE by reading SCISR with TDRE set and then writing to the SCI Data

•

0 = No character transferred to Transmit Shift register

•

1 = Character transferred to Transmit Shift register; Transmit Data register empty

10.9.4.2 Transmitter Idle Flag (TIDLE)—Bit 14

This bit is set when the TDRE flag is set and no data, preamble, or break character is being

transmitted. When TIDLE is set, the TXD pin becomes idle (Logic 1). Clear TIDLE by reading

the SCI Status Register (SCISR) with TIDLE set and then writing to the SCI Data Register

(SCIDR). TIDLE is not generated when a data character, a preamble, or a break is queued and

ready to be sent.

•

0 = Transmission in progress

•

1 = No transmission in progress

Base + $3

Read

TDRE TIDLE RDRF RIDLE

RAF

Write

Reset

000

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