DSP56857 datasheet(268/662 Pages) FREESCALE

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Interrupts

5685X Digital Signal Controller User Manual, Rev. 4

10-32

Freescale Semiconductor

10.12 Interrupts

10.12.1 Transmitter Empty Interrupt

This interrupt is enabled by setting the TEIE bit of the SCICR. When this interrupt is enabled an

interrupt is generated when data is transferred from the SCI Data register to the Transmit Shift

then write the next data to be transmitted to the SCIDR, clearing the TDRE bit.

10.12.2 Transmitter Idle Interrupt

This interrupt is enabled by setting the TIIE bit of the SCICR. This interrupt indicates the TDRE

flag is set and the transmitter is no longer sending data, preamble, or break characters. The

interrupt service routine should read the SCISR, verifying the TIDLE bit is set, then initiate a

preamble, break, or write a data character to the SCIDR. Any of these actions will clear the

TIDLE bit because the transmitter is busy at that time.

10.12.3 Receiver Full Interrupt

This interrupt is enabled by setting the RIE bit of the SCICR. This interrupt indicates the receive

data is available in the SCIDR. The interrupt service routine should read the SCISR, verifying the

RDRF bit is set, then read the data from the SCISR. This will clear the RDRF bit.

10.12.4 Receive Error Interrupt

This interrupt is enabled by setting the REIE bit of the SCICR. This interrupt indicates any of the

listed errors were detected by the receiver:

1. Noise Flag (NF) set

2. Parity error Flag (PF) set

Table 10-12. SCI Interrupt Sources

Interrupt Source

Flag

Local

Enable

Transmitter

TDRE

TEIE

Transmitter

TIDLE

TIIE

Receiver

RDRF

RFIE

Receiver

REIE

Receiver

RIDLE

RIIE

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