DSP56857 datasheet(266/662 Pages) FREESCALE

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SCI Register Descriptions (SCI0_BASE = $1FFFE0 and SCI1_BASE = $1FFDF8)

5685X Digital Signal Controller User Manual, Rev. 4

10-30

Freescale Semiconductor

10.9.4.7 Framing Error Flag (FE)—Bit 9

This bit is set when a Logic 0 is accepted as the Stop bit. FE bit is set during the same cycle as the

RDRF flag but it is not set in the case of an overrun. FE inhibits further data reception until it is

cleared. Clear FE by reading the SCISR with FE set, then write the

SCISR with any value.

•

0 = No framing error

•

1 = Framing error

10.9.4.8 Parity Error Flag (PF)—Bit 8

This bit is set when the Parity Enable (PE) bit is set and the parity of the received data does not

match its parity bit. Clear PF by reading the SCISR then write the SCISR with any value.

•

0 = No parity error

•

1 = Parity error

10.9.4.9 Reserved—Bits 7–1

These bits are reserved or not implemented. They are read as 0, but cannot be modified by

writing.

10.9.4.10 Receiver Active Flag (RAF)—Bit 0

This bit is set when the receiver detects a Logic 0 during the RT1 time period of the Start bit

search. RAF is cleared when the receiver detects false Start bits (usually from noise or baud rate

mismatch) or when the receiver detects a preamble.

•

0 = No reception in progress

•

1 = Reception in progress

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