DSP56857 datasheet(263/662 Pages) FREESCALE

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SCI Register Descriptions (SCI0_BASE = $1FFFE0 and SCI1_BASE = $1FFDF8)

Serial Communications Interface (SCI), Rev. 4

Freescale Semiconductor

10-27

10.9.2.16 Send Break (SBK)—Bit 0

Toggling SBK sends one break character (10 or 11 logic 0s). As long as SBK is set, the

transmitter sends logic 0s.

•

0 = No break characters

•

1 = Transmit break characters

10.9.3 SCI Control Register 2 (SCICR2)

This register can be read/written at anytime.

Figure 10-19. SCI Control Register 2 (SCICR2)

See Programmer’s Sheets on Appendix page B-57

10.9.3.1 Reserved—Bits 15–3

These bits are reserved or not implemented. They are read as 0, but cannot be modified by

writing.

10.9.3.2 Receiver Idle Interrupt Enable (RIIE)—Bit 2

This read/write RIIE bit is used to let the processor know a message has completed when using

DMA in a wake up mode of operation. The receiver is configured normally until a message is

detected. The processor code then determines if the message is for it. If so, DMA is enabled for

the maximum message size, and the RIIE interrupt is enabled to tell the core when the message

has completed. The receive DMA operation would be halted by the interrupt service routine at

this time.

10.9.3.3 Transmitter DMA Enable (TDE)—Bit 1

TDE enables DMA mode transfer of data from the SCIDR. For transmit DMA operation, this bit

must be set and a DMA channel must be configured to utilize the request.

•

0 = Transmit DMA disabled

•

1 = Transmit DMA enabled

Base + $2

Read

RIIE

TDE

RDE

Write

Reset

000

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