DSP56857 datasheet(257/662 Pages) FREESCALE

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DMA Operation

Serial Communications Interface (SCI), Rev. 4

Freescale Semiconductor

10-21

Enable Loop operation by setting the LOOP bit and clearing the RSRC bit in the SCI Control

Clearing the RSRC bit connects the transmitter output to the receiver input. Both the transmitter

and receiver must be enabled (TE = 1 and RE = 1).

10.7 DMA Operation

10.7.1 Transmit DMA Operation

Setting the TDE bit in SCICR2 enables Transmit DMA mode. In this mode, the Transmitter

Empty Interrupt is suppressed, allowing a transmitter DMA request to be generated. The DMA

controller can be configured to write to the SCIDR, clearing the TDRE and the DMA request.

10.7.2 Receive DMA Operation

Setting the RDE bit in SCICR2 enables Receiver DMA mode. In this mode, the Receiver Full

Interrupt is suppressed, allowing a Receiver DMA request to be generated. The DMA controller

can then be configured to read to the SCIDR, clearing the interrupt.

10.7.3 Receiver Wake Up with DMA

If DMA operation is desired during either of the wake up modes of operation, DMA requests

should only be made for a message addressed to the receiver. For example, Wake Up operation

proceeds normally until a desired receive message is identified. Then DMA requests are

generated to buffer the remainder of the message. An example of the DMA receive operations is

provided in Appendix 10-10, “Receiver Wake Up with DMA.” .

Table 10-10. Receiver Wake Up with DMA

1. Configure the SCI for standard receive operation

2. SCI receives the first frame of the incoming message and stores it in the SCIDR

3. A SCI Receiver Full interrupt occurs

4. The ISR looks at the message address information and determines:

MESSAGE NOT FOR US

MESSAGE IS FOR US

5. Configure SCI for RWU mode and wait for the end of the

message. Repeat from setup 1.

5. Enable DMA operation with a buffer large enough

to accommodate the max message size.

6. Enable RIIE so the SCI will interrupt at the

completion of the message. (Assumes the DMA

buffer does not fill up first.)

7. When the RII interrupt occurs, process the

message and return to setup 1.

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