DSP56857 datasheet(254/662 Pages) FREESCALE

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Functional Description

5685X Digital Signal Controller User Manual, Rev. 4

10-18

Freescale Semiconductor

With the misaligned character, shown in Figure 10-13, the receiver counts 170 RT cycles at the

point when the count of the transmitting device is10 bit

× 16 RT cycles + 3 RT

cycles = 163 RT cycles.

The maximum percent difference between the receiver count and the transmitter count of a slow

9-bit character with no errors is:

10.6.4.7 Fast Data Tolerance

Figure 10-14 demonstrates how much a fast received frame can be misaligned without causing a

noise error or a framing error. The fast Stop bit ends at RT10 instead of RT16 but it is still

sampled at RT8, RT9, and RT10.

Figure 10-14. Fast Data

For an 8-bit data character, data sampling of the Stop bit takes the receiver 9-bit

× 16 RT

cycles + 10 RT cycles = 154 RT cycles.

With the misaligned character shown in Figure 10-14, the receiver counts 154 RT cycles at the

point when the count of the transmitting device is 10 bit

× 16 RT cycles = 160 RT cycles.

The maximum percent difference between the receiver count and the transmitter count of a fast

8-bit character with no errors is:

For a 9-bit data character, data sampling of the stop bit takes the receiver 10 bit

× 16 RT

cycles + 10 RT cycles = 170 RT cycles.

With the misaligned character shown in Figure 10-14, the receiver counts 170 RT cycles at the

point when the count of the transmitting device is 11 bit

× 16 RT cycles = 176 RT cycles.

170

163

–

170

------------------------

100

4.12%

IDLE OR NEXT FRAME

STOP

DATA

SAMPLES

RECEIVER

RT CLOCK

154

160

–

154

------------------------

100

3.90%

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