DSP56857 datasheet(258/662 Pages) FREESCALE

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Low Power Modes

5685X Digital Signal Controller User Manual, Rev. 4

10-22

Freescale Semiconductor

10.8 Low Power Modes

10.8.1 Run Mode

Clearing the Transmitter Enable (TE) or Receiver Enable (RE) bits in the SCI Control Register

(SCICR) reduces power consumption in the Run mode. SCI registers are still accessible when TE

or RE is cleared, but clocks to the core of the SCI are disabled.

10.8.2 Wait Mode

SCI operation in the Wait mode depends on the state of the SWAI bit in the SCI Control Register

(SCICR).

•

If the SWAI bit is clear, the SCI operates normally when the Central Processing Unit (CPU)

is in the Wait mode.

•

If the SWAI bit is set, SCI clock generation ceases and the SCI module enters a

power-conservation state when the CPU is in the Wait mode. In this condition, SCI registers

are not accessible. Setting SWAI does not affect the state of the Receiver Enable (RE) bit or

the Transmitter Enable (TE) bit.

If the SWAI bit is set, any transmission or reception in progress stops at the Wait mode

entry. The transmission or reception resumes when either an internal or external interrupt

brings the digital signal controller out of the Wait mode. Exiting the Wait mode by reset

aborts any transmission or reception in progress and resets the SCI.

10.8.3 Stop Mode

The SCI is inactive in the Stop mode for reduced power consumption. The STOP instruction does

not affect SCI register states. SCI operation resumes after an external interrupt brings the CPU

out of the Stop mode. Exiting the Stop mode by reset aborts any transmission or reception in

progress and resets the SCI.

10.8.4 Wait Mode Recovery

Any enabled SCI interrupt request can bring the CPU out of the Wait mode.

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