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MSP432P411VIPZ bảng dữ liệu(PDF) 157 Page - Texas Instruments

tên linh kiện MSP432P411VIPZ
Giải thích chi tiết về linh kiện  SimpleLink Mixed-Signal Microcontrollers
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MSP432P411VIPZ bảng dữ liệu(HTML) 157 Page - Texas Instruments

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MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
www.ti.com
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Submit Documentation Feedback
Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V
Detailed Description
Copyright © 2017–2018, Texas Instruments Incorporated
(1)
X = Don't care
(2)
Not available on the 64-pin RGC package.
(3)
Direction controlled by eUSCI_B3 module.
(4)
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
6.12.5 Port P10 (P10.0 to P10.3) Input/Output With Schmitt Trigger
Port Schematic: see Figure 6-8
Table 6-67 lists the settings to select the port functions.
Table 6-67. Port P10 (P10.0 to P10.3) Pin Functions
PIN NAME (P10.x)
x
FUNCTION
CONTROL BITS OR SIGNALS (1)
P10DIR.x
P10SEL1.x
P10SEL0.x
P10.0/UCB3STE/L39 (2)
0
P10.0 (I/O)
I: 0; O: 1
0
0
UCB3STE
X (3)
0
1
L39 (4)
X
1
0
N/A
0
1
1
DVSS
1
P10.1/UCB3CLK/L38 (2)
1
P10.1 (I/O)
I: 0; O: 1
0
0
UCB3CLK
X (3)
0
1
L38 (4)
X
1
0
N/A
0
1
1
DVSS
1
P10.2/UCB3SIMO/UCB3SDA/L
37 (2)
2
P10.2 (I/O)
I: 0; O: 1
0
0
UCB3SIMO/UCB3SDA
X (3)
0
1
L37 (4)
X
1
0
N/A
0
1
1
DVSS
1
P10.3/UCB3SOMI/UCB3SCL/L
36 (2)
3
P10.3 (I/O)
I: 0; O: 1
0
0
UCB3SOMI/UCB3SCL
X (3)
0
1
L36 (4)
X
1
0
N/A
0
1
1
DVSS
1



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