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MSP432P411VIPZ bảng dữ liệu(PDF) 154 Page - Texas Instruments

tên linh kiện MSP432P411VIPZ
Giải thích chi tiết về linh kiện  SimpleLink Mixed-Signal Microcontrollers
PDF  212 Pages
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MSP432P411VIPZ bảng dữ liệu(HTML) 154 Page - Texas Instruments

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MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
Submit Documentation Feedback
Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V
Detailed Description
Copyright © 2017–2018, Texas Instruments Incorporated
(1)
X = Don't care
(2)
Direction controlled by eUSCI_A2 module.
(3)
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
(4)
Direction controlled by eUSCI_B2 module.
6.12.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
Port Schematic: see Figure 6-8
Table 6-65 lists the settings to select the port functions.
Table 6-65. Port P3 (P3.0 to P3.7) Pin Functions
PIN NAME (P3.x)
x
FUNCTION
CONTROL BITS OR SIGNALS (1)
P3DIR.x
P3SEL1.x
P3SEL0.x
P3MAPx
P3.0/PM_UCA2STE/L7
0
P3.0 (I/O)
I: 0; O: 1
0
0
X
UCA2STE
X (2)
0
1
default
L7 (3)
X
1
0
X
N/A
0
1
1
X
DVSS
1
P3.1/PM_UCA2CLK/L6
1
P3.1 (I/O)
I: 0; O: 1
0
0
X
UCA2CLK
X (2)
0
1
default
L6 (3)
X
1
0
X
N/A
0
1
1
X
DVSS
1
P3.2/PM_UCA2RXD/PM_U
CA2SOMI/L5
2
P3.2 (I/O)
I: 0; O: 1
0
0
X
UCA2RXD/UCA2SOMI
X (2)
0
1
default
L5 (3)
X
1
0
X
N/A
0
1
1
X
DVSS
1
P3.3/PM_UCA2TXD/PM_U
CA2SIMO/L4
3
P3.3 (I/O)
I: 0; O: 1
0
0
X
UCA2TXD/UCA2SIMO
X (2)
0
1
default
L4 (3)
X
1
0
X
N/A
0
1
1
X
DVSS
1
P3.4/PM_UCB2STE/L3
4
P3.4 (I/O)
I: 0; O: 1
0
0
X
UCB2STE
X (4)
0
1
default
L3 (3)
X
1
0
X
N/A
0
1
1
X
DVSS
1
P3.5/PM_UCB2CLK/L2
5
P3.5 (I/O)
I: 0; O: 1
0
0
X
UCB2CLK
X (4)
0
1
default
L2 (3)
X
1
0
X
N/A
0
1
1
X
DVSS
1
P3.6/PM_UCB2SIMO/PM_
UCB2SDA/L1
6
P3.6 (I/O)
I: 0; O: 1
0
0
X
UCB2SIMO/UCB2SDA
X (4)
0
1
default
L1 (3)
X
1
0
X
N/A
0
1
1
X
DVSS
1



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