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MSP432P411VIPZ bảng dữ liệu(PDF) 152 Page - Texas Instruments

tên linh kiện MSP432P411VIPZ
Giải thích chi tiết về linh kiện  SimpleLink Mixed-Signal Microcontrollers
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MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
Submit Documentation Feedback
Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V
Detailed Description
Copyright © 2017–2018, Texas Instruments Incorporated
(1)
X = Don't care
(2)
Direction controlled by eUSCI_A0 module.
(3)
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
(4)
Direction controlled by eUSCI_B0 module.
Table 6-63. Port P1 (P1.0 to P1.7) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
CONTROL BITS OR SIGNALS (1)
P1DIR.x
P1SEL1.x
P1SEL0.x
P1.0/UCA0STE/L19
0
P1.0 (I/O)
I: 0; O: 1
0
0
UCA0STE
X (2)
0
1
L19 (3)
X
1
0
N/A
0
1
1
DVSS
1
P1.1/UCA0CLK/L18
1
P1.1 (I/O)
I: 0; O: 1
0
0
UCA0CLK
X (2)
0
1
L18 (3)
X
1
0
N/A
0
1
1
DVSS
1
P1.2/UCA0RXD/UCA0SOMI/L
17
2
P1.2 (I/O)
I: 0; O: 1
0
0
UCA0RXD/UCA0SOMI
X (2)
0
1
L17 (3)
X
1
0
N/A
0
1
1
DVSS
1
P1.3/UCA0TXD/UCA0SIMO/L
16
3
P1.3 (I/O)
I: 0; O: 1
0
0
UCA0TXD/UCA0SIMO
X (2)
0
1
L16 (3)
X
1
0
N/A
0
1
1
DVSS
1
P1.4/UCB0STE/L15
4
P1.4 (I/O)
I: 0; O: 1
0
0
UCB0STE
X (4)
0
1
L15 (3)
X
1
0
N/A
0
1
1
DVSS
1
P1.5/UCB0CLK/L14
5
P1.5 (I/O)
I: 0; O: 1
0
0
UCB0CLK
X (4)
0
1
L14 (3)
X
1
0
N/A
0
1
1
DVSS
1
P1.6/UCB0SIMO/UCB0SDA/L
13
6
P1.6 (I/O)
I: 0; O: 1
0
0
UCB0SIMO/UCB0SDA
X (4)
0
1
L13 (3)
X
1
0
N/A
0
1
1
DVSS
1
P1.7/UCB0SOMI/UCB0SCL/L
12
7
P1.7 (I/O)
I: 0; O: 1
0
0
UCB0SOMI/UCB0SCL
X (4)
0
1
L12 (3)
X
1
0
N/A
0
1
1
DVSS
1



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