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MSP432P411VIPZ bảng dữ liệu(PDF) 160 Page - Texas Instruments

tên linh kiện MSP432P411VIPZ
Giải thích chi tiết về linh kiện  SimpleLink Mixed-Signal Microcontrollers
PDF  212 Pages
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MSP432P411VIPZ bảng dữ liệu(HTML) 160 Page - Texas Instruments

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P7.0/PM_SMCLK/PM_DMAE0/R03
PySEL1.x
PyDIR.x
PyIN.x
EN
To modules
From module
PyOUT.x
1
0
DVSS
DVCC
1
D
To LCD_F
Pad Logic
Bus
Keeper
Direction
0: Input
1: Output
PyREN.x
0 1
0 0
1 0
1 1
PySEL0.x
0 1
0 0
1 0
1 1
DVSS
DVSS
P7.1/PM_C0OUT/PM_TA0CLK/R13/LCDREF
P7.2/PM_C1OUT/PM_TA1CLK/R23
From LCD_F
160
MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
Submit Documentation Feedback
Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V
Detailed Description
Copyright © 2017–2018, Texas Instruments Incorporated
(1)
X = Don't care
(2)
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
6.12.7 Port P7 (P7.0 to P7.2) Input/Output With Schmitt Trigger
Figure 6-10 shows the port schematic. Table 6-69 lists the settings to select the port functions.
Figure 6-10. P7.0, P7.1 and P7.2 Port Schematic
Table 6-69. Port P7 (P7.0 to P7.2) Pin Functions
PIN NAME (P7.x)
x
FUNCTION
CONTROL BITS OR SIGNALS (1)
P7DIR.x
P7SEL1.x
P7SEL0.x
P7MAPx
P7.0/PM_SMCLK/
PM_DMAE0
R03
0
P7.0 (I/O)
I: 0; O: 1
0
0
X
DMAE0
0
0
1
default
SMCLK
1
R03 (2)
X
1
0
X
N/A
0
1
1
X
DVSS
1
P7.1/PM_C0OUT/
PM_TA0CLK
R13
1
P7.1 (I/O)
I: 0; O: 1
0
0
X
TA0CLK
0
0
1
default
C0OUT
1
R13 (2)
X
1
0
X
N/A
0
1
1
X
DVSS
1



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