TNETV2501INPGF datasheet(138/197 Pages) TI1

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Electrical Specifications

138

December 2002 − Revised November 2008

SPRS206K

5.4

Electrical Characteristics Over Recommended Operating Case Temperature

Range (Unless Otherwise Noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

DVDD = 3.3 ± 0.3 V, IOH = MAX

2.4

VOL

Low-level output voltage

IOL = MAX

0.4

IIZ

Input current for outputs in

Output-only or

input/output pins

with bus holders

Bus holders enabled

DVDD = MAX, VO = VSS to DVDD

− 300

300

IIZ

Input current for outputs in

high impedance

All other

output-only or

input/output pins

DVDD = MAX, VI = VSS to DVDD

− 5

µA

Input pins with

internal pulldown

DVDD = MAX, VI = VSS to DVDD

− 5

300

X2/CLKIN

DVDD = MAX, VI = VSS to DVDD

− 50

Input current

Input pins with

internal pullup

Pullup enabled

DVDD = MAX, VI = VSS to DVDD

− 300

µA

All other

input-only pins

DVDD = MAX, VI = VSS to DVDD

− 5

IDDC

CVDD supply current†

CVDD = Nominal

CPU clock = 300 MHz

TC = 25°C

239

IDDD

DVDD supply current†

DVDD = Nominal

CPU clock = 300 MHz

TC = 25°C

IDDP

PVDD supply current†

PVDD = Nominal

20-MHz clock input,

APLL mode = x15

Input capacitance

Output capacitance

† Current draw is highly application-dependent. The power numbers quoted here are for the sample application described in the

TMS320VC5501/02 Power Consumption Summary application report (literature number SPRA993). The spreadsheet provided with the

application report can be used to estimate the power consumption for a particular application. The spreadsheet also contains the current

consumption that can be expected when running the DSP in its idle configurations.

The sample application can be summarized as follows:

Case temperature: 25

°C

APLL: 300 MHz

CPU: 85% utilization

− Instruction cache enabled

− CLKOUT off

EMIF: 75 MHz, 118% utilization, 100% writes, 32 bits, 100% switching

− ECLKOUT1 and ECLKOUT2: Off

HPI: 5Mwords/second, 100% utilization, 100% writes, 100% switching

DMA:

− Channel 0: 35% utilization, 32-bit elements, 100% switching (for internal memory to external memory transfers)

− Channel 1: 1.56% utilization, 32-bit elements, 100% switching (for internal memory to McBSP0 transfers)

− Channel 2: 1.56% utilization, 32-bit elements, 100% switching (for McBSP1 to internal memory transfers)

− Channels 3 and 4: 0% utilization (reserved for UART transfers)

− Channel 5: 60% utilization (for internal memory to internal memory transfers using Watchdog Timer event)

McBSP0: 25 MHz, 100% utilization, 100% switching

Timer0: 5 MHz, 100% utilization, 100% switching

Timer1: 10 MHz, 100% utilization, 100% switching

WD Timer: 30 MHz, 100% utilization, 100% switching

UART: 9600 baud, 100% utilization

All other peripherals use 0 MHz, 0% utilization

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