TNETV2501INPGF datasheet(25/197 Pages) TI1

25 / 197 page

Introduction

December 2002 − Revised November 2008

SPRS206K

Table 2−4. Signal Descriptions (Continued)

Name

Function

Other‡

Type†

Multiplexed

Signal Name

Parallel Port − Control Pins (Continued)

I/O/Z

C, D, E,

F, G, H,

The C4 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO24 or external memory interface control signal

EMIF.CE0. The function of the C4 pin is determined by the state of the GPIO6 pin during

reset. The C4 pin is set to PGPIO24 if GPIO6 is low during reset. The C4 pin is set to

EMIF.CE0 if GPIO6 is high during reset. The function of the C4 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

PGPIO24

I/O/Z

F, G, H,

Parallel general-purpose I/O. PGPIO24 is selected when GPIO6 is low during reset.

The PGPIO24 signal is configured as an input after reset.

EMIF.CE0

O/Z

EMIF chip-select for memory space CE0. EMIF.CE0 is selected when GPIO6 is high

during reset. The EMIF.CE0 signal is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

I/O/Z

C, D, E,

F, G, H,

The C5 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO25 or external memory interface control signal

EMIF.CE1. The function of the C5 pin is determined by the state of the GPIO6 pin during

reset. The C5 pin is set to PGPIO25 if GPIO6 is low during reset. The C5 pin is set to

EMIF.CE1 if GPIO6 is high during reset. The function of the C5 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

PGPIO25

I/O/Z

F, G, H,

Parallel general-purpose I/O. PGPIO25 is selected when GPIO6 is low during reset.

The PGPIO25 signal is configured as an input after reset.

EMIF.CE1

O/Z

EMIF chip-select for memory space CE1. EMIF.CE1 is selected when GPIO6 is high

during reset. The EMIF.CE1 signal is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

I/O/Z

C, D, E,

F, G, H,

The C6 pin of the Parallel Port serves one of two functions: parallel general-purpose

input/output (PGPIO) signal PGPIO26 or external memory interface control signal

EMIF.CE2. The function of the C6 pin is determined by the state of the GPIO6 pin during

reset. The C6 pin is set to PGPIO26 if GPIO6 is low during reset. The C6 pin is set to

EMIF.CE2 if GPIO6 is high during reset. The function of the C6 pin will be set once the

device is taken out of reset (RESET pin transitions from a low to high state).

PGPIO26

I/O/Z

F, G, H,

Parallel general-purpose I/O. PGPIO26 is selected when GPIO6 is low during reset.

The PGPIO26 signal is configured as an input after reset.

EMIF.CE2

O/Z

EMIF chip-select for memory space CE2. EMIF.CE2 is selected when GPIO6 is high

during reset. The EMIF.CE2 signal is in a high-impedance state during reset and is set to

output after reset with an output value of 1.

† I = Input, O = Output, S = Supply, Z = High impedance

‡ Other Pin Characteristics:

A − Internal pullup [always enabled]

B − Internal pulldown [always enabled]

C − Hysteresis input

D − Pin has bus holder, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

E − Pin is high impedance in HOLD mode (due to HOLD pin). The EKxHZ bits in the EMIF Global Control Registers (EGCR1, EGCR2)

determine the state of the ECLKOUTx signals during HOLD mode. If EKxHZ = 0, ECLKOUTx continues clocking during HOLD mode.

If EKxHZ = 1, ECLKOUTx goes to high impedance during HOLD mode.

F − Pin is high impedance in OFF mode (TRST = 0, EMU0 = 1, and EMU1/OFF = 0).

G − Pin can be configured as a general-purpose input.

H − PIn can be configured as a general-purpose output.

− Pin has an internal pullup, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

K − Pin has an internal pulldown, it can be enabled/disabled through the External Bus Control Register (XBCR) [enabled by default].

− Fail-safe pin

M − Pin is in high-impedance during reset (RESET pin is low)

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