TNETV2501INPGF datasheet(43/197 Pages) TI1

43 / 197 page

Functional Overview

December 2002 − Revised November 2008

SPRS206K

•

Four timers

−

Two 64-bit general-purpose timers

−

A programmable watchdog timer

−

A DSP/BIOS timer

•

An Inter-integrated Circuit (I2C) multi-master and slave interface

•

A Universal Asynchronous Receiver/Transmitter (UART)

For detailed information on the C55x DSP peripherals, see the following documents:

•

TMS320VC5501/5502 DSP Instruction Cache Reference Guide (literature number SPRU630)

•

TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618)

•

TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module Reference Guide

(literature number SPRU146)

•

TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (literature number SPRU620)

•

TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide

(literature number SPRU613)

•

TMS320VC5501/5502/5503/5507/5509/5510 DSP Multichannel Buffered Serial Port (McBSP)

Reference Guide (literature number SPRU592)

•

TMS320VC5501/5502 DSP External Memory Interface (EMIF) Reference Guide

(literature number SPRU621)

•

TMS320VC5501/5502 DSP Universal Asynchronous Receiver/Transmitter (UART) Reference Guide

(literature number SPRU597)

3.3

Configurable External Ports and Signals

A number of pins on the 5501 have two functions, a feature that allows system designers to choose an

appropriate media interface for his/her application without the need for a large pin-count package. Two muxes

are included in the 5501 to control the configuration of these dual-function pins: the Parallel Port Mux and the

Host Port Mux. The state of these muxes is set at reset based on the state of the GPIO6 pin. The External

Bus Selection Register (XBSR) reflects the configuration of these muxes after the 5501 comes out of reset.

3.3.1 Parallel Port Mux

The Parallel Port Mux of the 5501 controls the function of 20 address signals (pins A[21:2]), 32 data signals

(pins D[31:0]), and 16 control signals (pins C0 through C15). The Parallel Port Mux supports two different

modes:

•

Full EMIF mode: The EMIF is enabled and its 20 address, 32 data, and 16 control signals are routed to

their corresponding pins on the Parallel Port Mux.

•

Parallel general-purpose I/O mode: The EMIF and HPI are disabled and 16 control, 4 address, and

16 data pins of the Parallel Port Mux are set to parallel general-purpose I/O (PGPIO).

The mode of the Parallel Port Mux is determined by the state of the GPIO6 pin at reset. If GPIO6 is low, the

EMIF and the HPI will be disabled: pins A[17:2] and pins D[15:0] will become reserved pins. All other pins in

the Parallel Port Mux are set to parallel general-purpose I/O. The Parallel/Host Port Mux Mode bit field in the

External Bus Selection Register (XBSR) will also be set to 0 to reflect the PGPIO mode of the Parallel Port

Mux.

If GPIO6 is high at reset, the HPI will be enabled in multiplexed mode and the EMIF will be fully enabled: pins

A[21:2] are set to EMIF.A[21:2], pins D[31:0] are set to EMIF.D[31:0], and pins C[15:0] are set to their

corresponding EMIF operation. The Parallel/Host Port Mux Mode bit field in the XBSR will be set to 1 to reflect

the full EMIF mode of the Parallel Port Mux. Note that in multiplexed mode, the HPI will use the HD[7:0] pins

to strobe in address and data information (see Section 3.7, Host-Port Interface (HPI), for more information on

the operation of the HPI in multiplexed mode).

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