DA9061 datasheet(74/82 Pages) DIALOG

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DA9061

Entry level PMIC for applications requiring up to 6 A

Datasheet

Revision 3.2

01-Mar-2016

CFR0011-120-00 Rev 5

74 of 82

Table 96: VLDO1_B (0x0BA)

Field

Slice

Description

Reset

LDO1_SL_B

7:7

Force LDO sleep mode if VLDO*_B is selected.

Reserved

6:6

Reserved

VLDO1_B

5:0

From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV

Less than 0x02: 0.90 V; greater than 0x38: 3.60 V

0x31

Table 97: VLDO2_B (0x0BB)

Field

Slice

Description

Reset

LDO2_SL_B

7:7

Force LDO sleep mode if VLDO*_B is selected.

Reserved

6:6

Reserved

VLDO2_B

5:0

From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV

Less than 0x02: 0.90 V; greater than 0x38: 3.60 V

0x31

Table 98: VLDO3_B (0x0BC)

Field

Slice

Description

Reset

LDO3_SL_B

7:7

Force LDO sleep mode if VLDO*_B is selected.

Reserved

6:6

Reserved

VLDO3_B

5:0

From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV

Less than 0x02: 0.90 V; greater than 0x38: 3.60 V

0x31

Table 99: VLDO4_B (0x0BD)

Field

Slice

Description

Reset

LDO4_SL_B

7:7

Force LDO sleep mode if VLDO*_B is selected.

Reserved

6:6

Reserved

VLDO4_B

5:0

From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV

Less than 0x02: 0.90 V; greater than 0x38: 3.60 V

0x31

A.3

PAGE 2

A.3.1

Customer trim and configuration

Table 100: INTERFACE (0x105)

Field

Slice

Description

Reset

IF_BASE_ADDR

7:4

2-WIRE slave address MSBs. The LSBs of the slave address

are “000”. The complete slave address is then

IF_BASE_ADDR * 2

3. However, the device also responds to

IF_BASE_ADDR * 2

3+1.

0xB

Reserved

3:0

Reserved

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