DA9061 datasheet(72/82 Pages) DIALOG

72 / 82 page

DA9061

Entry level PMIC for applications requiring up to 6 A

Datasheet

Revision 3.2

01-Mar-2016

CFR0011-120-00 Rev 5

72 of 82

Table 84: BUCK3_CFG (0x09F)

Field

Slice

Description

Reset

BUCK3_MODE

7:6

0: Controlled by B*_SL_A/B

1: Sleep

2: Synchronous

3: Automatic

BUCK3_PD_DIS

5:5

Disable pull-down resistor when disabled.

Reserved

4:0

Reserved

Table 85: BUCK2_CFG (0x0A0)

Field

Slice

Description

Reset

BUCK2_MODE

7:6

0: Controlled by B*_SL_A/B

1: Sleep

2: Synchronous

3: Automatic

BUCK2_PD_DIS

5:5

Disable pull-down resistor when disabled.

Reserved

4:0

Reserved

Table 86: VBUCK1_A (0x0A4)

Field

Slice

Description

Reset

BUCK1_SL_A

7:7

Force sync (0) / sleep (1) mode if B*_MODE==VSELCTL and

VB*_A is active.

VBUCK1_A

6:0

From 0.3 V (0x00) to 1.57 V (0x7F) in steps of 10 mV

0x50

Table 87: VBUCK3_A (0x0A5)

Field

Slice

Description

Reset

BUCK3_SL_A

7:7

Force sync (0) / sleep (1) mode if B*_MODE==VSELCTL and

VB*_A is active.

VBUCK3_A

6:0

From 0.53 V (0x00) to 1.8 V (0x7F) in steps of 10 mV

0x43

Table 88: VBUCK2_A (0x0A7)

Field

Slice

Description

Reset

BUCK2_SL_A

7:7

Force sync (0) / sleep (1) mode if B*_MODE==VSELCTL and

VB*_A is active.

VBUCK2_A

6:0

From 0.80 V (0x00) to 3.34 V (0x7F) in steps of 20 mV

0x14

Table 89: VLDO1_A (0x0A9)

Field

Slice

Description

Reset

LDO1_SL_A

7:7

Force LDO sleep mode if VLDO*_A is active.

Reserved

6:6

Reserved

VLDO1_A

5:0

From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV

Less than 0x02: 0.90 V; greater than 0x38: 3.60 V

0x31

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