DA9061 datasheet(52/82 Pages) DIALOG

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DA9061

Entry level PMIC for applications requiring up to 6 A

Datasheet

Revision 3.2

01-Mar-2016

CFR0011-120-00 Rev 5

52 of 82

ground. The quiet ground can then be connected to the main ground at the paddle, as shown in

Figure 19.

All traces carrying high discontinuous currents should be kept as short as possible.

Noise sensitive analog signals, such as feedback lines or crystal connections, should be kept away

from traces carrying pulsed analog or digital signals. This can be achieved by separation or shielding

with quiet signals or ground traces.

LDOs and switched mode supplies

8.2.2

The placement of the distributed capacitors on the VSYS rail must ensure that all VDD inputs and

VSYS are connected to a bypass capacitor close to the pad. It is recommended placing at least two

1 µF capacitors close to the VDD_LDOx pads and at least one 10 µF close to the VDD_BUCKx pads.

Using a local power plane underneath the device for VSYS might be considered.

Transient current loops in the area of the switching converters should be minimised.

The common references (IREF, VREF) should be placed close to the device and cross-coupling to

any noisy digital or analog trace must be avoided.

Output capacitors of the LDOs can be placed close to the input pins of the supplied devices (remote

from the DA9061).

Care must be taken with trace routing to ensure that no current is carried on feedback lines of the

buck output voltages (VBUCKx).

The inductor placement is less critical since parasitic inductances have negligible effect.

Optimising thermal performance

8.2.3

DA9061 features a ground paddle which should be connected with as many vias as possible to the

PCB’s main ground plane in order to achieve good thermal performance.

Solder mask openings for the ball landing pads must be arranged to prohibit solder balls flowing into

vias.

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