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PC87591L bảng dữ liệu(PDF) 161 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện PC87591L
Giải thích chi tiết về linh kiện  LPC Mobile Embedded Controllers
PDF  437 Pages
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nhà sản xuất  NSC [National Semiconductor (TI)]
Trang chủ  http://www.national.com
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PC87591L bảng dữ liệu(HTML) 161 Page - National Semiconductor (TI)

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Embedded Controller Modules (Continued)
Revision 1.07
161
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Status Register (USTAT)
This byte-wide, read-only register contains the receive and transmit status bits. The register is cleared (0016) on reset.
Location: 00 FD2616
Type: RO
Bit
76543210
Name
Reserved
XMIP
RB9
BKD
ERR
DOE
FE
PE
Reset
00000000
Bit
Description
0
PE. The bit is set when a parity error is detected within a received character. The bit is cleared by the hardware
when USTAT register is read.
0: No parity error detected
1: Parity error detected in a received byte since the last time USTAT was read
1
FE. The bit is set when the USART fails to receive a valid stop bit at the end of a frame. Automatically cleared
on read of USTAT.
0: No framing error detected
1: Framing error detected on a received byte since the last time USTAT was read
2
DOE. The bit is set when a new character is received and transferred to RBUF before the software has read the
previous character. Automatically cleared on read of the USTAT.
0: No data overrun error detected
1: Data overrun error detected since the last time USTAT was read
3
ERR. The bit is set any time DOE, FE or PE is set. Automatically cleared if DOE, FE and PE are all zero. This
bit is read only. Any attempt to write to the bit by software does not alter its present value.
0: No DOE, FE or PE has occurred since the last time USTAT register was read.
1: A DOE, FE or PE error has occurred since the last time USTAT register was read.
4
BKD. If set, indicates that a line break condition has occurred. A break condition is detected if RXD remains low
for a least ten bit times after a missing stop bit has been detected at the end of a frame. The bit is cleared under
the following conditions:
–
On a read of USTAT register, if the break condition on RXD is no longer present. If RXD is still low when USTAT
register is read, the bit is not cleared.
–
If the read of USTAT register did not cause the bit to be cleared because the break condition on RXD was still
in effect, the hardware clears the bit as soon as the break condition no longer exists, i.e., RXD returns to a high
level.
5
RB9. Contains the ninth data bit of the last frame received when operating with the 9-bit data format.
0: “0” received in ninth bit position
1: “1” received in ninth bit position
6
XMIP. Indicates that the USART is transmitting data. It is reset by hardware at the end of the last frame bit.
0: USART is not transmitting
1: USART is transmitting
7
Reserved.



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