PC87591L datasheet(340/437 Pages) NSC

340 / 437 page

6.0 Host-Controlled Modules and Host Interface (Continued)

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340

Revision 1.07

6.1.2

Standard Configuration Registers

SuperI/O Control and Conﬁguration Registers

The SuperI/O configuration registers at indexes 2016 and 2716 are mainly used for part identification, global power manage-

ment and the selection of pin multiplexing options. For details, see Section 6.1.8 on page 343.

Logical Device Control and Conﬁguration Registers

A subset of these registers is implemented for each logical device. See the functional block descriptions in Chapter 5 on

page 277 and Chapter 6 on page 335.

Control

The only implemented control register for each logical device is the Activate register at index 3016. Bit 0 of Activate register

controls the activation of the associated functional block. Activation enables access to the functional block’s registers and

attaches the functional block’s system resources (e.g., address space and interrupts), which are unused as long as the block

is not activated. Other effects may apply on a function-specific basis (such as clock enable and active pinout signaling).

SuperI/O Control and

Conﬁguration Registers

Logical Device Control and

one per Logical Device

Conﬁguration Registers -

Index

0716

Logical Device Number

2016

SuperI/O ID

2116

SuperI/O Conﬁguration 1

2516

SuperI/O Conﬁguration 5

2616

SuperI/O Conﬁguration 6

2716

SuperI/O Revision ID

2816

SuperI/O Conﬁguration 8

2916

SuperI/O Conﬁguration 9

2D16

SuperI/O Conﬁguration D

2B16 -2E16

Reserved exclusively for National use

3016

Logical Device Control (Activate)

6016

I/O Base Address Descriptor 0 Bits 15-8

6116

I/O Base Address Descriptor 0 Bits 7-0

6216

I/O Base Address Descriptor 1 Bits 15-8

6316

I/O Base Address Descriptor 1 Bits 7-0

7016

Interrupt Number and Wake-Up on IRQ Enable

7116

IRQ Type Select

7416

DMA Channel Select 0

7516

DMA Channel Select 1

F016 -F916

Device Speciﬁc Logical Device Conﬁguration 1 to 10

(some are optional)

Figure 110. Conﬁguration Register Map

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