PC87591L datasheet(300/437 Pages) NSC

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Host Controller Interface Modules (Continued)

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5.3.3

Indirect Memory Read and Write Transaction

The following I/O mapped registers can be utilized instead of memory mapping to perform a core bus transaction using an

LPC I/O transaction:

●

Four Indirect Memory Address registers (IMA3-IMA0), representing host address bits 31 to 0

●

One Indirect Memory Data register (IMD), representing data bits 7 to 0

An LPC I/O write to the IMD register triggers a core bus memory write cycle using the addresses and data from IMA3-IMA0

and IMD registers, respectively. The LPC I/O write is completed when the core bus transaction is completed.

An LPC I/O read cycle from IMD register triggers a core bus memory read cycle using the addresses from IMA3-IMA0. The

data returned from the core bus cycle is used to complete the LPC I/O read cycle from IMD register.

Read/write cycles from/to IMA3-IMA0 registers drive Short Wait on the Sync field. Read/write cycles from/to IMD register

drive Long Wait on the Sync ﬁeld until a transaction is actually performed and completed on the core bus.

Indirect memory read/write transactions are subject to the same memory mapping, locking mechanism and host access pro-

tection as memory and FWH memory read/write transactions. For more details, see Sections 5.3.2, 5.3.4 and 5.3.5.

5.3.4

Locking Between Domains

For read operations, hardware handles arbitration between the host and core. For program and erase operations, the

PC87591x provides the means for enabling exclusive use for any particular access path over a sequence of operations.

By default, the core has access permission to the on-chip flash, and the HLOCK bit is cleared (0). In this case, if a program

or erase operation starts, any host read operation is deferred or aborted, as defined by HERES field in SMCCST register.

When host erase or program operation is required, the Signaling interface (Section 5.3.7 on page 303) or one of the other

host/core communication channels should be used to request control of the flash from the core. The core should go into a

state in which the flash is not written or erased and then set the HLOCK bit. Note that core reads from the flash may be

delayed in this case; therefore, it is recommended for critical code to be copied to RAM. Once the host access to the flash

is completed, the host should indicate this to the core, allowing it to clear the HLOCK bit and resume normal operation.

00 000016

Main Block Top Address (MBTA)

1F FFFF16

F FFFF16

F FFFF16 - MBTA

0 000016

10 000016

00 E00016

01 000016

0 000016 - MBTA

Host Address

Core Address

Figure 101. Host to Core Address Translation: Non-BIOS Mode

Expansion Memory

On-Chip Flash

Reserved (Out-of-Range)

Numbers (1,2) indicate the links

between host memory and core

memory maps.

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