PC87591L datasheet(253/437 Pages) NSC

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Embedded Controller Modules (Continued)

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Flash ID Read

To identify the device version, perform the following sequence:

1. Enable flash access (if not already enabled).

2. Read the Device ID (SID and SRID register values), using the Device ID Scan, as follows:

a. Set the IR to Device ID Scan instruction.

b. Scan the LF_ID chain.

4.19.5 Test Access Port (TAP)

This section defines the top-level design of the TAP, as illustrated in Figure 81. Subsequent sections provide detailed TAP

design requirements.

The TAP includes the following elements:

●

TAP signals

●

TAP controller

●

Instruction Register (IR)

●

Data registers (Debugger and Flash interfaces).

The Instruction and data registers have separate shift register-based paths connected in parallel. These registers have a

common serial data input and a common serial data output connected to the TAP TDI and TDO signals, respectively.

The TAP controller selects between TDI and TDO as the alternative instruction and data register paths.

Figure 81. TAP Block Diagram

DBGDATA Register

Instruction Register

Instruction Decode

Output Buffer

TDI

TDO

Clocks and/or Controls

TAP Controller

TMS

TCK

DBGMASKS Register

BYPASS Register

FL_ADDR Register

FL_DATA Register

FL_ID Register

FL_CT_ST Register

FL_ERASE Register

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