CP3SP33SMSSLASHNOPB datasheet(306/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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The Bus Busy bit indicates the bus is busy. It is set when the bus is active (i.e., a low

level on either SDAn or SCLn) or by a Start Condition. It is cleared when the module is

disabled, on detection of a Stop Condition, or when writing 1 to this bit. See section

Section 29.6 Usage Notes for a description of the use of this bit.

0 – Bus is not busy.

1 – Bus is busy.

MATCH

The Address Match bit indicates in slave mode when ACBnADDR.SAEN is set and the

first seven bits of the address byte (the first byte transferred after a Start Condition)

matches the 7-bit address in the ACBnADDR register, or when ACBnADDR2.SAEN is

set and the first seven bits of the address byte matches the 7-bit address in the

ACBnADDR2 register. It is cleared by Start Condition or repeated Start and Stop

Condition (including illegal Start or Stop Condition).

0 – No address match occurred.

1 – Address match occurred.

GCMTCH

The Global Call Match bit is set in slave mode when the ACBnCTL1.GCMEN bit is set

and the address byte (the first byte transferred after a Start Condition) is 00h. It is

cleared by a Start Condition or repeated Start and Stop Condition (including illegal Start

or Stop Condition).

0 – No global call match occurred.

1 – Global call match occurred.

TSDA

The Test SDA bit samples the state of the SDAn signal. This bit can be used while

recovering from an error condition in which the SDAn signal is constantly pulled low by a

slave that went out of sync. This bit is a read-only bit. Data written to it is ignored.

TGSCL

The Toggle SCL bit enables toggling the SCLn signal during error recovery. When the

SDAn signal is low, writing 1 to this bit drives the SCn signal high for one cycle. Writing 1

to TGSCL when the SDAn signal is high is ignored. The bit is cleared when the clock

toggle is completed.

0 – Writing 0 has no effect.

1 – Writing 1 toggles the SDAn signal high for one cycle.

MATCHAF

The Match Address Field bit indicates which of two address fields matched the slave

address. If both fields match, the MATCHAF bit is cleared. The MATCHAF bit is cleared

by a Start condition, repeated Start condition, or Stop condition. Illegal Start and Stop

conditions also clear the MATCHAF bit.

0 – ACBnADDR.ADDR field matched the slave address.

1 – ACBnADDR2.ADDR field matched the slave address.

ARPMATCH

The ARP Address Match bit indicates when an ARP match occurs. This bit is set in slave

mode when ACBnCTL3.ARPEN is set and the address byte (first byte transferred after a

Start condition) is 110 0001b. The ARPMATCH bit is cleared by a Start condition,

repeated Start condition, or Stop condition. Illegal Start and Stop conditions also clear

the ARPMATCH bit.

0 – Slave address was not 110 0001b.

1 – ARP address match enabled, and slave address was 110 0001b.

29.5.4 ACBn Control Register 1 (ACBnCTL1)

The ACBnCTL1 registers are 8-bit, read/write registers that configure and control the ACB modules.

Following reset, Idle mode, Halt mode, and disabling the module, the ACBnCTL1 register is cleared.

STASTRE

NMINTE

GCMEN

ACK

DMAEN

INTEN

STOP

START

306

Dual ACCESS.bus Interfaces

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