CP3SP33SMSSLASHNOPB datasheet(308/407 Pages) TI1

308 / 407 page

CP3SP33

SNOSCW5 – MAY 2013

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STASTRE The Stall After Start Enable bit enables the stall after start mechanism. When enabled, the

ACB is stalled after the address byte. When the STASTRE bit is clear, the ACBnST.STASTR

bit is always clear.

0 – No stall after start.

1 – Stall-after-start enabled.

29.5.5 ACBn Control Register 2 (ACBnCTL2)

The ACBnCTL2 registers are 8-bit, read/write registers that control the module and select the ACB clock

rate. At reset, the ACBnCTL2 register is cleared.

SCLFRQ6:0

ENABLE

The Enable bit controls the ACB module. When this bit is set, the ACB module is enabled.

When the Enable bit is clear, the ACB module is disabled, the ACBnCTL1, ACBnST, and

ACBnCST registers are cleared, and the clocks are halted.

0 – ACB module disabled.

1 – ACB module enabled.

SCLFRQ6: The SCL Frequency field specifies the low 7 bits of the SCLn period (low time plus high

time) in master mode. The ACBnCTL3 register holds the high 2 bits. The clock low time and

high time are defined as follows:

tSCLl = tSCLh = 2 × SCLFRQ8:0 × tCLK in which tCLK is the PCLK Clock period. The

SCLFRQ8:0 field may have values in the range of 008h through 1FFh. Other values are

reserved.

29.5.6 ACBn Control Register 3 (ACBnCTL3)

The ACBnCTL3 registers are 8-bit, read/write registers that expand the clock prescaler field and enable

ARP matches. At reset, the ACBnCTL3 registers are cleared.

Reserved

ARPMEN

SCLFRQ8:7

ARPMEN

The ARP Match Enable bit enables the matching of an incoming address byte to the SMBus

ARP address 110 0001b general call address (Start condition followed by address byte of

00h), while the ACB is in slave mode.

0 – ACB does not respond to ARP addresses.

1 – ARP address matching enabled.

SCLFRQ

The SCL Frequency field specifies the SCL period (low time plus high time) in master mode.

The ACBnCTL3 register provides a 2-bit expansion of this field, with the remaining 7 bits

being held in the ACBnCTL2 register.

29.5.7 ACBn Own Address Register 1 (ACBnADDR1)

The ACBnADDR1 registers are 8-bit, read/write registers that hold the module’s first ACCESS.bus

address. After reset, their values are undefined.

SAEN

ADDR

308

Dual ACCESS.bus Interfaces

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