CP3SP33SMSSLASHNOPB datasheet(307/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

START

The Start bit is set to generate a Start Condition on the ACCESS.bus. The START bit is

cleared when the Start Condition is sent, or upon detection of a Bus Error (ACBnST.BER =

1). This bit should be set only when in Master mode, or when requesting Master mode. If this

device is not the active master of the bus (ACBnST.MASTER = 0), setting the START bit

generates a Start Condition as soon as the ACCESS.bus is free (ACBnCST.BB = 0). An

address send sequence should then be performed. If this device is the active master of the

bus (ACBnST.MASTER = 1), when the START bit is set, a write to the ACBnSDA register

generates a Start Condition, then the ACBnSDA data is transmitted as the slave’s address

and the requested transfer direction. This case is a repeated Start Condition. It may be used

to switch the direction of the data flow between the master and the slave, or to choose

another slave device without using a Stop Condition in between.

0 – Writing 0 has no effect.

1 – Writing 1 generates a Start condition.

STOP

The Stop bit in master mode generates a Stop Condition that completes or aborts the current

message transfer. This bit clears itself after the Stop condition is issued.

0 – Writing 0 has no effect.

1 – Writing 1 generates a Stop condition.

INTEN

The Interrupt Enable bit controls asserting ACB interrupts. When the INTEN bit is cleared,

interrupts are disabled. When the INTEN bit is set, interrupts are enabled.

0 – Interrupts disabled.

1 – Interrupts enabled.

An interrupt is asserted on any of the following events:

● An address MATCH is detected (ACBnST.NMATCH = 1) and the NMINTE bit is set.

● A Bus Error occurs (ACBnST.BERR = 1).

● Negative acknowledge after sending a byte (ACBnST.NEGACK = 1).

● If DMA is not enabled, an interrupt is asserted on acknowledgement of each transaction

(same as hardware setting the ACBnST.SDAST bit).

● If ACBnCTL1.STASTRE = 1, in master mode after a successful start (ACBnST.STASTR =

1).

● Detection of a Stop Condition while in slave receive mode (ACBnST.SLVSTP = 1).

DMAEN

The DMA Enable bit controls whether DMA requests are enabled. A DMA request is asserted

at the end of any data transaction (ACBnST.SDAST = 1). If INTEN is set, interrupts are

generated upon occurrence of any error or a new match).

0 – DMA requests disabled.

1 – DMA requests enabled.

ACK

The Acknowledge bit holds the value this device sends in master or slave mode during the

next acknowledge cycle. Setting this bit to 1 instructs the transmitting device to stop sending

data, since the receiver either does not need, or cannot receive, any more data. This bit is

cleared after the first acknowledge cycle. This bit is ignored when in transmit mode.

GCMEN

The Global Call Match Enable bit enables the match of an incoming address byte to the

general call address (Start Condition followed by address byte of 00h) while the ACB is in

slave mode. When cleared, the ACB does not respond to a global call.

0 – Global call matching disabled.

1 – Global call matching enabled.

NMINTE

The New Match Interrupt Enable controls whether ACB interrupts are generated on new

matches. Set the NMINTE bit to enable the interrupt on a new match (i.e., when

ACBnST.NMATCH is set). The interrupt is issued only if the ACBnCTL1.INTEN bit is set.

This bit must be set when using DMA for the data transfer.

0 – New match interrupts disabled.

1 – New match interrupts enabled.

Dual ACCESS.bus Interfaces

307

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