CP3SP33SMSSLASHNOPB datasheet(303/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

Check that the ACBnCST.BUSY bit is inactive before entering Power Save, Idle, or Halt mode. This

assures that the device does not acknowledge an address sent and stop responding later.

29.2.3 SDAn nand SCLn Pin Configuration

The SDA and SCL pins are driven as open-drain signals. Internal pullups may be enabled for either pin.

For more information, see the I/O configuration section.

29.2.4 ACB Clock Frequency Configuration

The ACB module permits software to select the frequency used for the ACCESS.bus clock. The clock

period is set by the ACBCTL2.SCLFRQ6:0 and ACBCTL3.SCLFRQ8:7 fields. Together, they form a 9-bit

value that specifies the SCL clock period. This clock low period may be extended by stall periods initiated

by the ACB module or by another ACCESS.bus device. In case of a conflict with another bus master, a

shorter clock high period may be forced by the other bus master until the conflict is resolved.

29.3 Interrupt Support

ACB module 0 uses IRQ23, and module 1 uses IRQ11.

Because the interrupt request for module 1 can be handled by either the CPU or DSP interrupt controllers,

the interrupt request is passed through the Audio Subsystem Controller (ASC), which is programmed to

route it to the interrupt controller. To use the interrupt, it must be enabled at three levels:

•

ACB module—the interrupt must be enabled in the ACBnCTL1 register.

•

ASC module—the interrupt is assigned to ASC interrupt channel 1, so bit 1 in the ASCINTSEL register

must be clear to select the CPU interrupt controller or set to select the DSP interrupt controller.

•

Interrupt controller—the interrupt request must be enabled in the interrupt controller. For the CPU

interrupt controller, this is interrupt request IRQ11.

29.4 SMA Support

ACB module 0 uses DMA request 35, and module 1 uses DMA request 20.

Because the module 1 DMA request can be handled by either the CPU or DSP DMA controllers, the DMA

request is passed through the Audio Subsystem Controller (ASC), which must be programmed to route it

to the DMA controller.

To use the DMA request, it must be enabled at three levels:

•

ACB module—the DMA request must be enabled.

•

ASC module—the DMA request is assigned to ASC DMA channel 20. This channel is controlled by bit

4 in the ASCDMASEL1 register. The bit must be clear to select the CPU DMA controller or set to

select the DSP DMA controller. If the DSP DMA controller is selected, the DSP DMA channel must be

enabled in the ASCDDMASELn registers.

•

DMA controller—the DMA request must be enabled in the DMA controller. For the CPU DMA

controller, this is DMA request 20.

29.5 ACCESS.bus Interface Registers

The ACCESS.bus interface uses the registers listed in Table 29-1.

Table 29-1. ACCESS.bus Interface Registers

NAME

ADDRESS

DESCRIPTION

ACB0SDA

FF 8000h

ACB0 Serial Data Register

ACB1SDA

FF 5400h

ACB1 Serial Data Register

ACB0ST

FF 8004h

ACB0 Status Register

ACB1ST

FF 5404h

ACB1 Status Register

Dual ACCESS.bus Interfaces

303

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