CP3SP33SMSSLASHNOPB datasheet(34/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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9.1

DSP Memory Spaces

The DSP has a four-bus architecture. Instructions are received on the 16-bit P bus, the DSP data memory

is accessed through the 16-bit X and Y buses, and external memory and DSP peripherals are accessed

through the Z bus. Word addressing is used for all buses. Table 9-1 shows the mapping of the DSP data

memory space.

Table 9-1. DSP Data Memory Map

ADDRESS RANGE

BUS

DESCRIPTION

0000h to 17FFh

On-chip 6K-word data memory

1800h to DFFFh

Available for mapping to the external memory bus

8000h to 87FFh

Memory-mapped I/O registers used by peripherals that are only directly accessible by the DSP.

(Default address after reset)

The base address of this region can be reprogrammed by the DSP software.

E000h to F7FFh

On-chip 6K-word data memory

F800h to FFFFh

Available for mapping to the external memory bus

The DSP program space is implemented as two blocks, as shown in Table 9-2. While the DSP executes

from one block, the other block can be accessed by the DMA controller without degrading DSP

performance.

Table 9-2. DSP Program Memory Map

ADDRESS RANGE

DESCRIPTION

0000h to 0FFFh

4K-word program memory block

1000h to 3FFFh

Reserved

4000h to 5FFFh

8K-word program memory block

6000h to FFFFh

Reserved

The DSP accesses peripherals shared with the CPU indirectly, through the DSP DMA controller or the

memorymapped I/O registers (MMIO).

9.2

CPU/DSP Interface

The CPU has read and write access to the entire DSP data memory space (X, Y, Z), and write access to

the DSP program memory space. The CPU/DSP interface makes use of the DSP DMA controller to avoid

interrupting the DSP when servicing the CPU. The interface is hardcoded to use DSP DMA channel 0 for

DMA transfers between its FIFOs and DSP memory. This DMA channel has a slave interface on the CPU

peripheral data bus.

The CPU/DSP interface also includes hardware features to support interprocessor communications such

as a command/reply interface and semaphores. It also provides mechanisms for the CPU and DSP to

interrupt each other.

Data is transferred between the CPU and the DSP memory spaces through a set of indirect address and

data registers. An auto-increment address function eliminates the need to resend the address for every

word transferred. By default, the number of transactions is limited to 65535 (the default DMA transfer

size). The interface contains a 16-word read FIFO and a 16-word write FIFO to buffer transfers. These

FIFOs can be programmed to generate interrupts to the CPU on particular events (full, empty, etc.).

Additionally, the PBUSY bit in the ADMAS register indicates when the interface cannot accept another

access, for example if the write FIFO is full or a new operation is initiated before the current one

completes.

The CPU/DSP interface cannot be used when HCLK Clock or PCLK Clock is faster than DSP clock.

DSP and Audio Peripherals

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