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CP3SP33SMS/NOPB bảng dữ liệu(PDF) 46 Page - Texas Instruments

tên linh kiện CP3SP33SMS/NOPB
Giải thích chi tiết về linh kiện  Connectivity Processor with Cache, DSP, and Bluetooth짰, USB, and Dual CAN Interfaces
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CP3SP33SMS/NOPB bảng dữ liệu(HTML) 46 Page - Texas Instruments

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XCSn
HCLK
DS415
XAn
XWE
XBEn
XDn
Data
Address
tAS
tWR
tWP
CP3SP33
SNOSCW5 – MAY 2013
www.ti.com
Figure 10-2 shows the timing of a write cycle on the external memory bus.
Figure 10-2. Write Cycle Timing
An 8-level write buffer allows the EBIU to accept a write cycle and release the bus master (CPU, DSP, or
one of the DMA controllers) to continue execution without waiting for the write data to propagate to
external memory.
A read cycle is not allowed to propagate to external memory while there are any writes pending in the
write buffer. The read cycle is stalled until the write buffer has been flushed to memory. This mechanism
enforces memory coherency when the target of a read is modified by a pending write. In some cases,
software performance can be optimized by grouping writes together (for example, by loop unrolling) to
avoid alternating between reads and writes.
46
External Bus Interface Unit
Copyright © 2013, Texas Instruments Incorporated
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