CP3SP33SMSSLASHNOPB datasheet(302/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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29.2.2 Slave Node

A slave device waits in Idle mode for a master to initiate a bus transaction. Whenever the ACB is enabled

with a clear ACBnST.MASTER bit, it acts as a slave device.

Once a Start Condition on the bus is detected, this device checks whether the address sent by the current

master matches either:

•

ACBnADDR.ADDR, if the ACBnADDR.SAEN bit is set.

•

ACBnADDR2.ADDR, if the ACBnADDR2.SAEN bit is set.

•

The general call address, if the ACBnCTL1.GCM bit is set.

•

The global ARP address, if the ACBnCTL3.ARPMEN bit is set.

This match is checked even when the ACBnST.MASTER bit is set. If a bus conflict (on SDAn or SCLn) is

detected, the ACBnST.BER bit is set, the ACBnST.MASTER bit is cleared, and this device continues to

search the received message for a match. If an address match, ARP match, or a global match, is

detected:

1. This device asserts its data pin during the acknowledge cycle.

2. The ACBnCST.MATCH, ACBnCST.MATCHAF (or ACBnCST.GCMTCH if it is a global call address

match, or ACBnCST.ARPMATCH if it is an ARP address), and ACBnST.NMATCH in the ACBnCST

set to indicate that the buffer is empty.

3. If the ACBnCTL1.INTEN bit is set, an interrupt is asserted if both the INTEN and NMINTE bits in the

ACBnCTL1 register are set.

4. Software then reads the ACBnST.XMIT bit to identify the direction requested by the master device. It

clears the ACBnST.NMATCH bit so future byte transfers are identified as data bytes.

29.2.2.1 Slave Receive and Transmit

Slave Receive and Transmit are performed after a match is detected and the data transfer direction is

identified. After a byte transfer, the ACB extends the acknowledge clock until software reads or writes the

ACBnSDA register. The receive and transmit sequence are identical to those used in the master routine.

29.2.2.2 Slave Bus Stall

When operating as a slave, this device stalls the ACCESS.bus by extending the first clock cycle of a

transaction in the following cases:

1. The ACBnST.SDAST bit is set.

2. The ACBnST.NMATCH, and ACBnCTL1.NMINTE bits are set.

29.2.2.3 Slave Error Detections

The ACB detects illegal Start and Stop Conditions on the ACCESS.bus (i.e., a Start or Stop Condition

within the data transfer or the acknowledge cycle). When an illegal Start or Stop Condition is detected, the

BER bit is set and the MATCH and GMATCH bits are cleared, causing the module to be an unaddressed

slave.

29.2.2.4 Power Down

When this device is in Power Save, Idle, or Halt mode, the ACB module is not active but retains its status.

If the ACB is enabled (ACBnCTL2.ENABLE = 1) on detection of a Start Condition, a wake-up signal is

issued to the MIWU module. Use this signal to switch this device to Active mode.

The ACB module cannot check the address byte for a match following the start condition that caused the

wake-up event for this device. The ACB responds with a negative acknowledge, and the device should

resend both the Start Condition and the address after this device has had time to wake up.

302

Dual ACCESS.bus Interfaces

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