CP3SP33SMSSLASHNOPB datasheet(304/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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Table 29-1. ACCESS.bus Interface Registers (continued)

NAME

ADDRESS

DESCRIPTION

ACB0CST

FF 8008h

ACB0 Control Status Register

ACB1CST

FF 5408h

ACB1 Control Status Register

ACB0CTL1

FF 800Ch

ACB0 Control Register 1

ACB1CTL1

FF 540Ch

ACB1 Control Register 1

ACB0CTL2

FF 8014h

ACB0 Control Register 2

ACB1CTL2

FF 5414h

ACB1 Control Register 2

ACB0CTL3

FF 801Ch

ACB0 Control Register 3

ACB1CTL3

FF 541Ch

ACB1 Control Register 3

ACB0ADDR1

FF 8010h

ACB0 Own Address Register 1

ACB1ADDR1

FF 5410h

ACB1 Own Address Register 1

ACB0ADDR2

FF 8018h

ACB0 Own Address Register 2

ACB1ADDR2

FF 5418h

ACB1 Own Address Register 2

29.5.1 ACBn Serial Data Register (ACBnSDA)

The ACBnSDA registers are 8-bit, read/write shift registers used to transmit and receive data. The most

significant bit is transmitted (received) first and the least significant bit is transmitted (received) last.

Reading or writing the ACBnSDA registers is allowed when ACBnST.SDAST is set; or for repeated starts

after setting the START bit. An attempt to access the register in other cases produces unpredictable

results.

DATA

29.5.2 ACBn Status Register (ACBnST)

The ACBnST registers are 8-bit, read/write registers that indicate the ACB status. The NMATCH,

STASTR, NEGACK, BER, and SLVSTP bits may be cleared by writing 1 to them. Writing 0 has no effect

on these bits. Following reset, Idle mode, Halt mode, and disabling the module, these registers are clear.

SLVSTP

SDAST

BER

NEGACK

STASTR

NMATCH

MASTER

XMIT

The Direction Bit bit is set when the ACB module is currently in master/slave transmit mode.

Otherwise it is cleared.

0 – Receive mode.

1 – Transmit mode.

MASTER

The Master bit indicates that the module is currently in master mode. It is set when a

request for bus mastership succeeds. It is cleared upon arbitration loss (BER is set) or the

recognition of a Stop Condition.

0 – Slave mode.

1 – Master mode.

NMATCH

The New match bit is set when the address byte following a Start Condition, or repeated

starts, causes a match or a global-call match. The NMATCH bit is cleared when written with

1. Writing 0 to NMATCH is ignored. If the ACBnCTL1.INTEN bit is set, an interrupt is sent

when this bit is set. When NMATCH is set DMA requests are not asserted.

0 – No match.

1 – Match or global-call match.

304

Dual ACCESS.bus Interfaces

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