CP3SP33SMSSLASHNOPB datasheet(310/407 Pages) TI1

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Interrupt

(IRQ69)

DS445

5-Bit Clock Divider

16-Bit Prescaler

(RTPRD)

32-Bit Counter

(RTCLD/RTCRD)

Compare Register 2

(RTCCMP2)

Compare Register 3

(RTCCMP3)

Compare Register 1

(RTCCMP1)

Interrupt Enable

32.768 kHz

Slow Clock

1 Hz Clock

(Typ.)

Reset

1024 Hz

Clock (Typ.)

Wake-Up Input

(WUI63)

Wake-Up Input

(WUI62)

Wake-Up Input

(WUI61)

CP3SP33

SNOSCW5 – MAY 2013

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•

In some cases, the bus may get stuck with the SCLn or SDAn lines active. A possible cause is an

erroneous Start or Stop Condition that occurs in the middle of a slave receive session. When the SCLn

signal is stuck active, there is nothing that can be done, and it is the responsibility of the module that

holds the bus to release it. When the SDAn signal is stuck active, the ACB module enables the release

of the bus by using the following sequence. Note that in normal cases, the SCLn signal may be toggled

only by the bus master. This protocol is a recovery scheme which is an exception that should be used

only in the case when there is no other master on the bus. The recovery procedure is as follows:

1. Disable and re-enable the module to set it into the not addressed slave mode

2. Set the ACBnCTL1.START bit to make an attempt to issue a Start Condition.

3. Check if the SDAn signal is active (low) by reading ACBnCST.TSDA bit. If it is active, issue a single

SCLn cycle by writing 1 to ACBnCST.TGSCL bit. If the SDAn line is not active, continue from

step 5.

4. Check if the ACBnST.MASTER bit is set, which indicates that the Start Condition was sent. If not,

repeat step 3 and 4 until the SDAn signal is released.

5. Clear the BB bit. This enables the START bit to be executed. Continue according to section

Section 29.2.1.8 Bus Idle Error Recovery

30 Real Time Clock

The Real Time Clock module (RTC) implements a 32-bit counter with a 16-bit programmable prescaler,

driven by the 32.768 kHz Slow Clock through a 5-bit clock divider, as shown in Figure 30-1. This provides

a time base with a long wraparound period (over 136 years) and the ability to schedule long-duration time

delays and periodic interrupts. Three compare registers are implemented: one register for asserting an

interrupt on wraparound of the programmable prescaler and two registers for asserting interrupts when the

32-bit counter reaches specified values.

The RTC is typically programmed to divide a 32.768 kHz Slow Clock by 32, which provides a 1024 Hz

clock input to the 16-bit prescaler. The prescaler is typically programmed for division by 1024, resulting in

a 1 Hz clock input to the 32-bit counter. However, the RTC can operate with a different Slow Clock

frequency, an input clock divisor of 1, 2, 4, 8, 16, or 32, and any integer prescaler divisor between 1 and

65,536 (decimal).

Figure 30-1. Real Time Clock

310

Real Time Clock

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