CP3SP33SMSSLASHNOPB datasheet(309/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

ADDR

The Own Address field holds the first 7-bit ACCESS.bus address of this device. When in slave

mode, the first 7 bits received after a Start Condition are compared to this field (first bit received

to bit 6, and the last to bit 0). If the address field matches the received data and the SAEN bit is

set, a match is detected.

SAEN

The Slave Address Enable bit controls whether address matching is performed in slave mode.

When set, the SAEN bit indicates that the ADDR field holds a valid address and enables the

match of ADDR to an incoming address byte. When cleared, the ACB does not check for an

address match.

0 – Address matching disabled.

1 – Address matching enabled.

29.5.8 ACBn Own Address Register 2 (ACBnADDR2)

The ACBnADDR2 registers are 8-bit, read/write registers that hold the module’s second ACCESS.bus

address. After reset, their values are undefined.

SAEN

ADDR

The Own Address field holds the second 7-bit ACCESS.bus address of this device. When in

slave mode, the first 7 bits received after a Start Condition are compared to this field (first bit

received to bit 6, and the last to bit 0). If the address field matches the received data and the

SAEN bit is set, a match is detected.

SAEN

The Slave Address Enable bit controls wheth- er address matching is performed in slave mode.

When set, the SAEN bit indicates that the ADDR field holds a valid address and enables the

match of ADDR to an incoming address byte. When cleared, the ACB does not check for an

address match.

0 – Address matching disabled.

1 – Address matching enabled.

29.6 Usage Notes

•

When the ACB module is disabled, the ACBnCST.BB bit is cleared. After enabling the ACB

(ACBnCTL2.ENABLE = 1) in systems with more than one master, the bus may be in the middle of a

transaction with another device, which is not reflected in the BB bit. There is a need to allow the ACB

to synchronize to the bus activity status before issuing a request to become the bus master, to prevent

bus errors. Therefore, before issuing a request to become the bus master for the first time, software

should check that there is no activity on the bus by checking the BB bit after the bus allowed timeout

period.

•

When waking up from power down, before checking the ACBnCST.MATCH bit, test the

ACBnCST.BUSY bit to make sure that the address transaction has finished.

•

The BB bit is intended to solve a deadlock in which two, or more, devices detect a usage conflict on

the bus and both devices cease being bus masters at the same time. In this situation, the BB bits of

both devices are active (because each deduces that there is another master currently performing a

transaction, while in fact no device is executing a transaction), and the bus would stay locked until

some device sends a ACBnCTL1.STOP condition. The ACBnCST.BB bit allows software to monitor

bus usage, so it can avoid sending a STOP signal in the middle of the transaction of some other

device on the bus. This bit detects whether the bus remains unused over a certain period, while the BB

bit is set.

Dual ACCESS.bus Interfaces

309

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