CP3SP33SMSSLASHNOPB datasheet(267/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

CVF

The CVSD Out FIFO Full bit set indicates whether the CVSD Out FIFO has been written by

the CVSD converter while the FIFO was already full. If the CVSDERRINT bit is set, an

interrupt will be asserted when the CVF bit is set. The CVF bit is cleared when the

CVSTATn register is read, unless the device is in Freeze mode.

0 – CVSD Out FIFO has not been written while full.

1 – CVSD Out FIFO has been written while full.

CVINST

The CVSD In FIFO Status field indicates the current number of empty 16-bit word locations

in the CVSD In FIFO. The field is biased by 1, so when there are 8 empty words (FIFO is

empty), the CVINST field will read as 111b. When there are 1 or 0 empty words (FIFO holds

7 or 8 words of data), the CVINST field will read as 000b.

CVOUTST CVSD Out FIFO Status field indicates the current number of valid 16-bit CVSD data words

in the CVSD Out FIFO. When the FIFO is empty, the CVOUTST field will read as 000b.

When the FIFO holds 7 or 8 words of data, the CVOUTST field will read as 111b.

27 Dual/Quad UART

The CP3SP33 provides four Universal Asynchronous Receiver/Transmitter (UART) modules in the FBGA-

224 package, and two UART modules in the FBGA-144 package. Each module supports a wide range of

software-programmable baud rates (up to 3.072 Mbaud) and data formats. It handles automatic parity

generation and several error detection schemes.

All UART modules offer the following features:

•

Full-duplex double-buffered receiver/transmitter

•

Asynchronous operation

•

Programmable baud rate

•

Programmable framing formats: 7, 8, or 9 data bits; even, odd, or no parity; one or two stop bits (mark

or space)

•

Hardware parity generation for data transmission and parity check for data reception

•

Interrupt or DMA requests on transmit ready and receive ready conditions, separately enabled

•

Software-controlled break transmission and detection

•

Internal diagnostic capability

•

Automatic detection of parity, framing, and overrun errors

The UART modules are referred to as UART0, UART1, UART2, and UART3. UART2 and UART3 are not

available in the FBGA-144 package.

UART0, UART1, and UART2 reside on the CPU peripheral APB bus. UART3 is on the shared audio

peripheral APB bus.

UART0 offers synchronous operation using the CKX external clock pin in the FBGA-224 package. The

CKX signal is not available in the FBGA-144 package.

UART0, UART1, and UART2 support hardware flow control using the CTSn and RTSn signals.

27.1 Functional Overview

Figure 27-1 is a block diagram of the UART module showing the basic functional units in the UART:

•

Transmitter

•

Receiver

•

Baud Rate Generator

•

Control and Error Detection

The Transmitter block consists of an 8-bit transmit shift register and an 8-bit transmit buffer. Data bytes

are loaded in parallel from the buffer into the shift register and then shifted out serially on the TXDn pin.

Dual/Quad UART

267

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