CP3SP33SMSSLASHNOPB datasheet(264/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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PCMIN

26.12.4 PCM Data Output Register (PCMOUTn)

The PCMOUTn registers are 16-bit, read-only registers. They are used to read PCM data from the CVSD

to PCM converter. They are double-buffered, providing a 125 µs period for an interrupt or DMA request to

respond. After reset the PCMOUT registers are clear.

PCMOUT

26.12.5 Logarithmic PCM Data Input Register n (LOGINn)

The LOGINn registers are 8-bit, write-only registers. They are used to receive 8-bit logarithmic PCM data

from the APB bus and convert it into 13-bit linear PCM data.

26.12.6 Logarithmic PCM Data Output Register n (LOGOUTn)

The LOGOUTn registers are 8-bit, read-only registers. They hold logarithmic PCM data that has been

converted from linear PCM data. After reset, the LOGOUT registers are clear.

LOGOUT

26.12.7 Linear PCM Data Input Register n (LINEARINn)

The LINEARINn registers are 16-bit, write-only registers. The data is left-aligned. When converting to A-

law, bits 2:0 are ignored. When converting to µ-law, bits 1:0 are ignored

LINEARIN

26.12.8 Linear PCM Data Output Register n (LINEAROUTn)

The LINEAROUTn registers are 16-bit, read-only registers. The data is left-aligned. When converting from

A-law, bits 2:0 are clear. When converting from µ-law, bits 1:0 are clear. After reset, this register is clear.

LINEAROUT

26.12.9 CVSD Control Register n (CVCTRLn)

The CVCTRLn registers are 16-bit, read/write registers that control interrupts, DMA, and modes of

operation. At reset, all implemented bits are cleared.

DMAPO

DMACI

DMACO

CVSDERRINT

CVSDINT

PCMINT

CLKEN

CVEN

14 13

Reserved

RESOLUTION

PCMCONV

CVSDCONV

DMAPI

264

Dual CVSD/PCM Conversion Modules

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