CP3SP33SMSSLASHNOPB datasheet(262/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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The number of DMA transfers required to service the CVSD buffer in Bluetooth RAM must be specified in

the DMA block length register. When the required number of DMA transfers has been executed, the DMA

controller will not acknowledge further DMA requests on the CVSDIN0 channel. The CVSD/PCM module

will suspend operation just before the end of the current CVSD decoding cycle. When a new CVSD buffer

becomes available, then the outstanding DMA requests will be acknowledged and the CVSD/PCM module

will restart.

When the CVSDOUT0 FIFO contains 5 entries or more, a DMA transfer is requested. If CVSDIN0 is

assigned to device A and the DIR bit in the DMA channel control register is clear, the DMA controller

reads data from the CVSDOUT0 register (device A) and writes the data into the Bluetooth RAM (device

B).

26.10 Bus Bandwidth and Latency Considerations

The DMA controller has a burst buffer, which can be enabled on a per-channel basis. When the buffer is

enabled, DMA operations occur as four-cycle burst transfers. These burst transfers optimize bus

bandwidth, because they eliminate extra cycles used to arbitrate for control of the bus (as compared to

four single-cycle transfers).

However, burst mode is not recommended for audio data because of its impact on latency. Three

additional data words will be needed to fill the buffer, so for example at an 8 ksps rate, 3 × 125 ms = 375

ms additional latency.

Latency may also be impacted by competition with the CPU and DSP for access to shared resources such

as the shared RAM and the external bus interface. However, the bandwidth required even for high-quality

audio signals is quite low compared to the bandwidth available from the on-chip buses. For example, a

DMA transfer between two peripherals for a 48 ksps audio channel on an APB bus operating at half the

speed of the CPU or DSP core bus would require 6 × 48000 = 0.288M core bus cycles/second. Compared

to the 96M core bus cycles/second available on the CPU and DSP buses, this is a very small number. It

can become significant, however, if the core buses are operated at low clock rates to reduce power

consumption.

When the CPU and DSP both attempt to access the same device at the same time, the CPU has priority.

Access to slow external devices by the CPU or DSP will not block on-chip peripheral-to-peripheral or

peripheral-to-memory DMA transfers. because the EBIU has a write buffer to shield the on-chip buses

from external bus write latency and the core buses are split-transaction buses, so external bus reads from

slow devices are non-blocking.

26.11 Freeze Mode

When Freeze mode is entered, the CVSD/PCM converters will exhibit the following behavior:

•

CVSD In FIFO will not have data removed by the converter core.

•

CVSD Out FIFO will not have data added by the converter core.

•

PCM Out buffer will not be updated by the converter core.

•

The automatic clear-on-read function of the following status bits in the CVSTATn register is disabled:

–

PCMINT

–

CVE

–

CVF

262

Dual CVSD/PCM Conversion Modules

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