CP3SP33SMSSLASHNOPB datasheet(266/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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PCMCONV

The PCM to PCM Conversion Format bit selects the PCM format for PCM/PCM

conversions.

0 – Linear PCM <-> 8-bit µ-Law PCM

1 – Linear PCM <-> 8-bit A-Law PCM

RESOLUTION

The Linear PCM Resolution field specifies the attenuation of the PCM data for the

linear PCM to CVSD conversions by right shifting and sign extending the data. This

affects the log PCM data as well as the linear PCM data. The log data is converted to

either left-justified zero-stuffed 13-bit (A-law) or 14-bit (µ-law). The RESOLUTION

field can be used to compensate for any change in average levels resulting from this

conversion.

00 – No shift.

01 – 1-bit attenuation.

10 – 2-bit attenuation.

11 – 3-bit attenuation.

26.12.10 CVSD Status Register n (CVSTATn)

The CVSTATn registers are 16-bit, read-only registers that hold the status information of the CVSD/PCM

modules. At reset or when the module is disabled (CVCTRLn.CVEN bit is cleared), all implemented bits

are cleared.

11 10

8 7

Reserved

CVOUTST

CVINST

CVF

CVE

PCMINT

CVNF

CVNE

The CVSD In FIFO Nearly Empty bit indicates when only three CVSD data words are left in

the CVSD In FIFO, so new CVSD data should be written into the CVSD In FIFO. If the

CVSDINT bit is set, an interrupt will be asserted when the CVNE bit is set. If the DMACI bit

is set, a DMA request will be asserted when this bit is set. The CVNE bit is cleared when

the CVSTATn register is read.

0 – CVSD In FIFO is not nearly empty.

1 – CVSD In FIFO is nearly empty.

CVNF

The CVSD Out FIFO Nearly Full bit indicates when only three empty word locations are left

in the CVSD Out FIFO, so the CVSD Out FIFO should be read. If the CVSDINT bit is set, an

interrupt will be asserted when the CVNF bit is set. If the DMACO bit is set, a DMA request

will be asserted when this bit is set. Software must not rely on the CVNF bit as an indicator

of the number of valid words in the FIFO. Software must check the CVOUTST field to read

the number of valid words in the FIFO. The CVNF bit is cleared when the CVSTATn register

is read.

0 – CVSD Out FIFO is not nearly full.

1 – CVSD Out FIFO is nearly full.

PCMINT

The PCM Interrupt bit set indicates that the PCMOUTn register is full and needs to be read

or the PCMINn register is empty and needs to be loaded with new PCM data. The PCMINT

bit is cleared when the CVSTATn register is read, unless the device is in Freeze mode.

0 – PCM does not require service.

1 – PCM requires loading or unloading.

CVE

The CVSD In FIFO Empty bit indicates when the CVSD In FIFO has been read by the

CVSD converter while the FIFO was already empty. If the CVSDERRINT bit is set, an

interrupt will be asserted when the CVE bit is set. The CVE bit is cleared when the

CVSTATn register is read, unless the device is in Freeze mode.

0 – CVSD In FIFO has not been read while empty.

1 – CVSD In FIFO has been read while empty.

266

Dual CVSD/PCM Conversion Modules

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