CP3SP33SMSSLASHNOPB datasheet(270/407 Pages) TI1

270 / 407 page

CKX

TXD

RXD

Sample Input

DS346

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

27.2.2 Synchronous Mode

The synchronous mode of UART0 enables the device to communicate with other devices using three

communication signals: transmit, receive, and clock. In this mode, data bits are transferred synchronously

with the UART0 clock signal. Data bits are transmitted on the rising edges and received on the falling

edges of the clock signal, as shown in Figure 27-3. Data bytes are transmitted and received least

significant bit (LSB) first.

Figure 27-3. UART Synchronous Communication

In synchronous mode, the transmit shift register (TSFT) and the transmit buffer (U0TBUF) double-buffer

the data for transmission. To transmit a character, a data byte is loaded in the U0TBUF register. The data

is then transferred to the TSFT register. The TSFT register shifts out one bit of the current character, LSB

first, on each rising edge of the clock. While the TSFT is shifting out the current character on the TXD0

pin, the U0TBUF register may be loaded by software with the next byte to be transmitted. When the TSFT

finishes transmission of the last stop bit within the current frame, the contents of U0TBUF are transferred

to the TSFT register and the Transmit Buffer Empty bit (UTBE) is set. The UTBE bit is automatically reset

by the UART when software loads a new character into the U0TBUF register. During transmission, the

UXMIP bit is set by the UART. This bit is cleared only after the UART has sent the last frame bit of the

current character and the U0TBUF register is empty.

The receive shift register (RSFT) and the receive buffer (URBUF) double-buffer the data being received.

Serial data received on the RXD0 pin is shifted into the RSFT register on the first falling edge of the clock.

Each subsequent falling edge of the clock causes an additional bit to be shifted into the RSFT register.

The UART assumes a complete character has been received after the correct number of rising edges on

CKX (based on the selected frame format) have been detected. On receiving a complete character, the

contents of the RSFT register are copied into the U0RBUF register and the Receive Buffer Full bit (URBF)

is set. The URBF bit is automatically cleared when software reads the character from the U0RBUF

The transmitter and receiver may be clocked by either an external source provided to the CKX pin or the

internal baud rate generator. In the latter case, the clock signal is placed on the CKX pin as an output.

27.2.3 Attention Mode

The Attention mode is available for networking this device with other processors. This mode requires the

9-bit data for- mat with no parity. The number of start bits and number of stop bits are programmable. In

this mode, two types of 9-bit characters are sent on the network: address characters consisting of 8

address bits and a 1 in the ninth bit position and data characters consisting of 8 data bits and a 0 in the

ninth bit position.

270

Dual/Quad UART

Submit Documentation Feedback

Product Folder Links :CP3SP33

CP3SP33SMS/NOPB bảng dữ liệu(PDF) 270 Page - Texas Instruments

CP3SP33SMS/NOPB bảng dữ liệu(HTML) 270 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL