CP3SP33SMSSLASHNOPB datasheet(268/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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The Receiver block consists of an 8-bit receive shift register and an 8-bit receive buffer. Data is received

serially on the RXDn pin and shifted into the shift register. Once eight bits have been received, the

contents of the shift register are transferred in parallel to the receive buffer.

The Transmitter and Receiver blocks both contain extensions for 9-bit data transfers, as required by the 9-

bit and loopback operating modes.

The Baud Rate Generator generates the clock for the synchronous and asynchronous operating modes. It

consists of two registers and a two-stage counter. The registers are used to specify a prescaler value and

a baud rate divisor. The first stage of the counter divides the UART clock based on the value of the

programmed prescaler to create a slower clock. The second stage of the counter creates the baud rate

clock by dividing the output of the first stage based on the programmed baud rate divisor.

The Control and Error Detection block contains the UART control registers, control logic, error detection

circuit, parity generator/checker, and interrupt generation logic. The control registers and control logic

determine the data format, mode of operation, clock source, and type of parity used. The error detection

circuit generates parity bits and checks for parity, framing, and overrun errors.

The Flow Control Logic block provides the capability for hardware handshaking between the UART and a

peripheral device. When the peripheral device needs to stop the flow of data from the UART, it deasserts

the clear-to-send (CTSn) signal which causes the UART to pause after sending the current frame (if any).

The UART asserts the ready-to-send (RTSn) signal to the peripheral when it is ready to send a character.

27.2 UART Operation

The UART has two basic modes of operation: synchronous and asynchronous. Synchronous mode is only

supported for the UART0 module. In addition, there are two special-purpose modes, called attention and

diagnostic. This section describes the operating modes of the UART.

27.2.1 Asynchronous Mode

The asynchronous mode of the UART enables the device to communicate with other devices using just

two communication signals: transmit and receive.

In asynchronous mode, the transmit shift register (TSFT) and the transmit buffer (UnTBUF) double-buffer

the data for transmission. To transmit a character, a data byte is loaded in the UnTBUF register. The data

is then transferred to the TSFT register. While the TSFT register is shifting out the current character (LSB

first) on the TXD pin, the UnTBUF register is loaded by software with the next byte to be transmitted.

When TSFT finishes transmission of the last stop bit of the current frame, the contents of UnTBUF are

transferred to the TSFT register and the Transmit Buffer Empty bit (UTBE) is set. The UTBE bit is

automatically cleared by the UART when software loads a new character into the UnTBUF register. During

transmission, the UXMIP bit is set high by the UART. This bit is reset only after the UART has sent the

last stop bit of the current character and the UnTBUF register is empty. The UnTBUF register is a

read/write register. The TSFT register is not software accessible.

In asynchronous mode, the input frequency to the UART is 16 times the baud rate. In other words, there

are 16 clock cycles per bit time. In asynchronous mode, the baud rate generator is always the UART clock

source.

The receive shift register (RSFT) and the receive buffer (UnRBUF) double buffer the data being received.

The UART receiver continuously monitors the signal on the RXDn pin for a low level to detect the

beginning of a start bit. On sensing this low level, the UART waits for seven input clock cycles and

samples again three times. If all three samples still indicate a valid low, then the receiver considers this to

be a valid start bit, and the remaining bits in the character frame are each sampled three times, around

the mid-bit position. For any bit following the start bit, the logic value is found by majority voting, i.e. the

two samples with the same value define the value of the data bit. Figure 27-2 illustrates the process of

start bit detection and bit sampling.

268

Dual/Quad UART

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