CP3SP33SMSSLASHNOPB datasheet(265/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

CVEN

The Module Enable bit enables or disables the CVSD conversion module interface.

When the bit is set, the interface is enabled which allows read and write operations to

the rest of the module. When the bit is clear, the module is disabled. When the

module is disabled the status register CVSTAT will be cleared to its reset state.

0 – CVSD module enabled.

1 – CVSD module disabled.

CLKEN

The CVSD Clock Enable bit enables the 2-MHz clock to the filter engine and CVSD

encoders and decoders.

0 – CVSD module clock disabled.

1 – CVSD module clock enabled.

PCMINT

The PCM Interrupt Enable bit controls generation of the PCM interrupt. If set, this bit

enables the PCM interrupt. If the PCMINT bit is clear, the PCM interrupt is disabled.

0 – PCM interrupt disabled.

1 – PCM interrupt enabled.

CVSDINT

The CVSD FIFO Interrupt Enable bit controls generation of the CVSD interrupt. If set,

this bit enables the CVSD interrupt that occurs if the CVSD In FIFO is nearly empty or

the CVSD Out FIFO is nearly full. If the CVSDINT bit is clear, the CVSD nearly

full/nearly empty interrupt is disabled.

0 – CVSD interrupt disabled.

1 – CVSD interrupt enabled.

CVSDERRINT

The CVSD FIFO Error Interrupt Enable bit controls generation of the CVSD error

interrupt. If set, this bit enables an interrupt to occur when the CVSD Out FIFO is full

or the CVSD In FIFO is empty. If the CVSDERRINT bit is clear, the CVSD full/empty

interrupt is disabled.

0 – CVSD error interrupt disabled.

1 – CVSD error interrupt enabled.

DMACO

The DMA Enable for CVSD Out bit enables hardware DMA control for reading CVSD

data from the CVSD Out FIFO. If clear, DMA support is disabled.

0 – CVSD output DMA disabled.

1 – CVSD output DMA enabled.

DMACI

The DMA Enable for CVSD In bit enables hardware DMA control for writing CVSD

data into the CVSD In FIFO. If clear, DMA support is disabled.

0 – CVSD input DMA disabled.

1 – CVSD input DMA enabled.

DMAPO

The DMA Enable for PCM Out bit enables hardware DMA control for reading PCM

data from the PCMOUT register. If clear, DMA support is disabled.

0 – PCM output DMA disabled.

1 – PCM output DMA enabled.

DMAPI

The DMA Enable for PCM In bit enables hardware DMA control for writing PCM data

into the PCMIN register. If cleared, DMA support is disabled.

0 – PCM input DMA disabled.

1 – PCM input DMA enabled.

CVSDCONV

The CVSD to PCM Conversion Format field specifies the PCM format for CVSD/PCM

conversions.

00 – CVSD <-> 8-bit µ-Law PCM.

01 – CVSD <-> 8-bit A-Law PCM.

10 – CVSD <-> Linear PCM.

11 – Reserved.

Dual CVSD/PCM Conversion Modules

265

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