CP3SP33SMSSLASHNOPB datasheet(261/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

The operation of the CVSD/PCM module (i.e., PCMINn to CVSDOUTn) is controlled by DMA

request/acknowledge activity on the CVSDOUTn and CVSDINn DMA channels. The number of DMA

transfers required to fill the CVSD buffer resident in Bluetooth RAM must be programmed into the DMA

controllers block length register. When the required number of DMA transfers has been executed, the

DMA controller will not acknowledge further DMA requests on the CVSDOUTn channel. Similarly, the

DMA requests on the CVSDINn channel are no longer acknowledged when the terminal count is reached

on the CVSDINn DMA operation. If a DMA request on either the CVSDOUTn or CVSDINn channel

remains unacknowledged, the CVSD/PCM module will suspend operation just before the end of the

current CVSD encoding cycle. When new CVSD data becomes available, the outstanding DMA requests

will be acknowledged and the CVSD/PCM module will restart.

26.9.2.2 PCM Receive Path

The CVSD/PCM modules have DMA channels assigned to their PCMOUTn registers. The DMA data

transfers from the CVSD/PCM modules to system RAM use indirect transfer, in which each transfer is

performed with two adjacent bus cycles (read/write). The operation of the PCMOUT0 DMA channel of

CVSD/PCM module 0 is described below. The PCMOUT1 DMA channel operates in a similar way.

The CVSD/PCM module requests a DMA transfer each time a new PCM sample is available in

PCMOUT0. If PCMOUT0 is assigned to device A and the DIR bit in the DMA channel control register is

clear, the DMA controller reads data from the PCMOUT0 register (device A) and writes the data into

system RAM (device B). The DMA controller must be configured so that automatic update of the device A

(PCMOUT0) address is disabled. The address of device B (system RAM) must be configured to

automatically increment or decrement by 2 after each DMA transfer.

The operation of the CVSD/PCM module (i.e. CVSDINn to PCMOUTn) is controlled by DMA

request/acknowledge activity on the CVSDINn and CVSDOUTn DMA channels. The number of DMA

transfers required to fill the PCM transmit buffer in system RAM must be specified in the DMA block length

acknowledge further DMA requests on the PCMINn channel. Similarly, further requests on the CVSDINn

and CVSDOUTn channels will not be acknowledged when the terminal count is reached on their DMA

transfers. The CVSD/PCM module will suspend operation when DMA requests on the CVSDINn or

CVDOUTn channels are no longer acknowledged by the DMA controller.

The CVSD/PCM module requires 250 clock cycles of the Auxiliary Clock to decode a PCM sample. The

frequency of the Auxiliary Clock determines the rate at which DMA requests are made on the PCMOUTn

Channel.

26.9.2.3 CVSD Transmit/Receive Paths

The CVSD/PCM modules operate in their free-running mode with DMA channels assigned to their

CVSDINn and CVSDOUTn registers. Activity on these DMA channels is linked to the CVSDINn and

CVSDOUTn FIFOs. The operation of the CVSD/PCM module 0 channels is described below. The

CVSD/PCM module 1 channels operate in a similar way.

Initially when the CVSD/PCM module 0 is enabled and a DMA request on CVSDIN0 is asserted, a 16-bit

CVSD-encoded data word is transferred from memory to the CVSDIN0 FIFO. Further DMA requests are

asserted each time the CVSDIN0 FIFO is read by the CVSD/PCM converter. The CVSD/PCM converter

requires 250 clock cycles of the Auxiliary Clock 2 (Auxiliary Clock 3 for CVSD/PCM module 1) to produce

a single PCM sample. The effective compression ratio of 2:1 results in a 16-bit word of CVSD data every

500 auxiliary clock cycles. At the start of each decoding cycle (500 auxiliary clock cycles), a DMA request

is made to transfer a CVSD-encoded data word from Bluetooth RAM to the CVSDIN0 FIFO. The

frequency of the auxiliary clock determines the time interval between successive DMA requests.

Dual CVSD/PCM Conversion Modules

261

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