CP3SP33SMSSLASHNOPB datasheet(259/407 Pages) TI1

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CVSD/PCM Converter 0

CVSDIN0

CVSDOUT0

PCMOUT0

PCMIN0

CVSDIN1

CVSDOUT1

PCMOUT1

PCMIN1

ATDR1

ARDR1

ATDR0

ARDR0

DS435

AAI

CVSD/PCM Converter 1

Bluetooth RAM

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

Figure 26-3. Dual CVSD Channels to AAI

26.9.1.1 PCM Transmit Data Path

The two AAI receive registers, ARDR0 and ARDR1, receive codec data for transmission over a Bluetooth

link. These registers are assigned to separate DMA channels. The DMA data transfers from the AAI to the

CVSD/PCM modules use indirect transfers, in which each transfer consists of two adjacent bus cycles

(read/write). The operation of the ARDR0 DMA channel is described below. The ARDR1 DMA channel

operates in a similar way.

The AAI requests a DMA transfer when ARDR0 is full. If ARDR0 is assigned to Device A and the DIR bit

in the DMA channel control register is clear, the DMA controller reads data from ARDR0 (device A) and

writes

the

data

into

the

PCMIN

CVSD0

(device

B).

Automatic

address

update

(increment/decrement) must be disabled. With an audio sample rate of 8 ksps, ARDR0 will request a DMA

transfer every 125 ms (every 1500 CPU clock cycles at a 12 MHz PCLK Clock rate).

26.9.1.2 PCM Receive Data Path

The two AAI transmit registers, ATDR0 and ATDR1, are assigned to separate DMA channels. The DMA

data transfers from the CVSD/PCM modules to the audio interface use indirect transfers, in which each

transfer consists of two adjacent bus cycles (read/write). The operation of the ATDR0 DMA channel is

described below. The ARDR1 DMA channel operates in a similar way.

The AAI requests a DMA transfer when ATDR0 is empty. If ATDR0 is assigned to Device A and the DIR

bit in the DMA channel control register is set, then the DMA controller reads data from the PCMOUT

(increment/decrement) must be disabled.

With an audio sample rate of 8 ksps, ATDR0 will request a DMA transfer every 125 ms (every 1500 CPU

clock cycles at a 12 MHz PCLK Clock rate).

26.9.1.3 CVSD Transmit/Receive Paths

The CVSD/PCM modules operate in their fixed-rate mode with DMA channels assigned to their CVSDINn

and CVSDOUTn registers. The activation of these DMA channels is linked to the operation of the

CVSDINn and CVSDOUTn FIFOs. The operation of the CVSD/PCM module 0 DMA channels is described

below. The CVSD/PCM module 1 DMA channels operate in a similar way.

Initially when the CVSDIN0 FIFO contains 3 or fewer entries, a single DMA transfer is requested. Further

DMA requests are generated each time the CVSDIN0 FIFO is read by the CVSD/PCM converter. If

CVSDIN0 is assigned to device A and the DIR bit in the DMA channel control register is set, the DMA

controller reads data from the Bluetooth RAM (device B) and writes the data into CVSDIN0 (device A).

The DMA channel must be configured so that automatic update of the device A (CVSDIN0) address is

disabled. The address of device B (Bluetooth RAM) must be configured to automatically increment or

decrement by 2 after each DMA transfer.

Dual CVSD/PCM Conversion Modules

259

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