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CP3SP33SMS/NOPB bảng dữ liệu(PDF) 255 Page - Texas Instruments

tên linh kiện CP3SP33SMS/NOPB
Giải thích chi tiết về linh kiện  Connectivity Processor with Cache, DSP, and Bluetooth짰, USB, and Dual CAN Interfaces
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CP3SP33
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SNOSCW5 – MAY 2013
26.2 PCM Conversions
During conversion between CVSD and PCM, any PCM format changes are done automatically depending
on whether the PCM data is µ-Law, A-Law, or linear. In addition to this, a separate function can be used to
convert between the various PCM formats as required. Conversion is performed by setting up the control
bit CVCTRLn.PCMCONV to define the conversion and then writing to the LOGINn and LINEARINn
registers and reading from the LOGOUTn and LINEAROUTn registers. There is no delay in the
conversion operation, and it does not have to operate at a fixed rate. It will only convert between µ-Law/A-
Law and linear, not directly between µ-Law and A-Law. (This could easily be performed by converting
between µ-Law and linear and between linear and A-Law.)
If a conversion is performed between linear and µ-Law log PCM data, the linear PCM data are treated in
the left-aligned 14-bit linear data format with the two LSBs unused. If a conversion is performed between
linear and A-Law log PCM data, the linear PCM data are treated in the left-aligned 13-bit linear data
format with the three LSBs unused.
If the module is only used for PCM conversions, the CVSD clock can be disabled by clearing the CVSD
Clock Enable bit (CLKEN) in the control register.
26.3 CVSD Conversion
The CVSD/PCM converter module transforms either 8-bit logarithmic or 13-bit to 16-bit linear PCM
samples at a fixed rate of 8 ksps. The CVSD to PCM conversion format must be specified by the
CVSDCONV control bits in the CVSD Control register (CVCTRLn).
The CVSD algorithm is designed for 2’s complement 16-bit data and is tuned for best performance with
typical voice data. Mild distortion will occur for peak signals greater than -6 dB. The Bluetooth CVSD
standard is designed for best performance with typical voice signals: nominally –6 dB with occasional
peaks to 0 dB rather than full-scale inputs. Distortion of signals greater than –6 dB is not considered
detrimental to subjective quality tests for voice-band applications and allows for greater clarity for signals
below –6 dB. The gain of the input device should be tuned with this in mind.
If required, the RESOLUTION field of the CVCTRLn register can be used to optimize the level of the 16-bit
linear input data by providing attenuations (right-shifts with sign extension) of 1, 2, or 3 bits.
Log data is always 8 bit, but to perform the CVSD conversion, the log data is first converted to 16-bit 2’s
complement linear data. A-law and µ-law conversion can also slightly affect the optimum gain of the input
data. The CVCTRL.RESOLUTION field can be used to attenuate the data if required.
If the resolution is not set properly, the audio signal may be clipped or attenuated.
26.4 Fixed-Rate PCM-to-CVSD Conversion
The converter core reads the double-buffered PCMIN register every 125 µs and writes a new 16-bit CVSD
data stream into the CVSD Out FIFO every 250 µs. If the PCMIN buffer has not been updated with a new
PCM sample between two reads from the CVSD core, the old PCM data is used again to maintain a fixed
conversion rate. Once a new 16-bit CVSD data stream has been calculated, it is copied into the 8 × 16-bit
wide CVSD Out FIFO.
If there are only three empty words (16-bit) left in the FIFO, the nearly full bit (CVNF) is set, and, if
enabled (CVSDINT = 1), an interrupt request is asserted.
If the CVSD Out FIFO is full, the full bit (CVF) is set, and, if enabled (CVSDERRINT = 1), an interrupt
request is asserted. In this case, the CVSD Out FIFO remains unchanged.
Within the interrupt handler, the CPU can read out the new CVSD data. If the CPU reads from an already
empty CVSD Out FIFO, a lockup of the FIFO logic may occur which persists until the next reset. Software
must check the CVOUTST field of the CVSTAT register to read the number of valid words in the FIFO.
Software must not use the CVNF bit as an indication of the number of valid words in the FIFO.
Copyright © 2013, Texas Instruments Incorporated
Dual CVSD/PCM Conversion Modules
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