CP3SP33SMSSLASHNOPB datasheet(253/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

RXSTATUSL The Receive FIFO Status Left Channel field indicates the current fill level of the left

channel receive FIFO. This field is not sticky, so an overrun condition may disappear

before software reads this field. Use the RXERIRQ bit to determine whether a FIFO

overrun has occurred. The RXST bit in the I2SRXCTL register controls the interpretation

of this field.

RXSTATUSL FIELD

RXST BIT

DESCRIPTION

1Fh

Overrun error (written while full)

1Eh

Underrun error (read while empty)

00h to 08h

0 to 8 empty words

00h to 08h

0 to 8 filled words

WSSTAT

The Word Select Status field indicates the length of one phase of the word select signal

I2SSWS in terms of the number of periods of the I2S bus clock I2SCLK. This is useful in

slave mode, so that software can determine the number of bits being sent by the master.

25.3.5 I

2S Receiver Left Channel Data Register (I2SRXDATALEFT)

The I2SRXDATALEFT register is a 32-bit, read-only register used to unload the left channel receive FIFO.

At reset, this register is initialized to 0000 000h.

Reserved

25.3.6 I

2S Receiver Right Channel Data Register (I2SRXDATARIGHT)

The I2SRXDATARIGHT register is a 32-bit, read-only register used to unload the right channel receive

FIFO. At reset, this register is initialized to 0000 000h.

Reserved

25.3.7 I

2S Transmitter Left Channel Data Register (I2STXDATALEFT)

The I2STXDATALEFT register is a 32-bit, write-only register used to load the left channel transmit FIFO.

At reset, this register is initialized to 0000 000h.

Reserved

25.3.8 I

2S Transmitter Right Channel Data Register (I2STXDATARIGHT)

The I2STXDATARIGHT register is a 32-bit, write-only register used to load the right channel transmit

FIFO. At reset, this register is initialized to 0000 000h.

Reserved

26 Dual CVSD/PCM Conversion Modules

The CVSD/PCM modules perform conversion between CVSD data and PCM data, in which the CVSD

encoding is that used in Bluetooth communication and the PCM encoding may be 8-bit µ-Law, 8-bit A-

Law, or 13-bit to 16-bit linear.

A CVSD module can operate in either of two modes:

Dual CVSD/PCM Conversion Modules

253

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