CP3SP33SMSSLASHNOPB datasheet(256/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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26.5 Fixed-Rate CVSD-to-PCM Conversion

The converter core reads from the CVSD In FIFO every 250 µs and writes a new PCM sample into the

PCMOUT buffer every 125 µs. If the previous PCM data has not yet been transferred to the audio

interface, it will be overwritten with the new PCM sample.

If there are only three unread words left, the CVSD In Nearly Empty bit (CVNE) is set and, if enabled

(CVSDINT = 1), an interrupt request is generated.

If the CVSD In FIFO is empty, the CVSD In Empty bit (CVE) is set and, if enabled (CVSDERRINT = 1), an

interrupt request is generated. If the converter core reads from an already empty CVSD In FIFO, the FIFO

automatically returns a checkerboard pattern to specify a minimum level of distortion of the audio stream.

26.6 Free-Running Mode

The free-running mode of the CVSD/PCM converter is enabled by setting the CVFR, DMACI, and DMACO

bits of the CVSD Control Register (CVCTRL). In this mode, the CVSD/ PCM converter is expected to be

serviced by DMA operations on both its PCM and CVSD input and output channels. In contrast to the

fixed-rate operating mode, the clock frequency for free-running operation is not restricted to 2 MHz. In

free-running mode, activity within the CVSD/PCM transcoder is governed by the acknowledgment of DMA

requests on the CVSDIN and CVSDOUT channels. If a DMA request on either of these channels goes

unacknowledged then the CVSD/PCM module will stall its internal operation just before the start of the

next transcoding cycle. When the outstanding DMA requests are eventually acknowledged then the

CVSD/PCM module will resume its operation in a seamless fashion.

26.7 Interrupt Generation

An interrupt is asserted in any of the following cases:

•

When a new PCM sample has been written into the PCMOUT register and the CVCTRLn.PCMINT bit

is set.

•

When a new PCM sample has been read from the PCMIN register and the CVCTRLn.PCMINT bit is

set.

•

When the CVSD In FIFO is nearly empty (CVSTATn.CVNE = 1) and the CVCTRLn.CVSDINT bit is set.

•

When the CVSD Out FIFO is nearly full (CVSTATn.CVNF = 1) and the CVCTRLn.CVSDINT bit is set.

•

When the CVSD In FIFO is empty (CVSTATn.CVE = 1) and the CVCTRLn.CVSDERRINT bit is set.

•

When the CVSD Out FIFO is full (CVSTATn.CVF = 1) and the CVCTRLn.CVSDERRINT bit is set

Both the CVSD In and CVSD Out FIFOs have a size of 8 bit × 16 bit (8 words). The warning limits for the

two FIFOs are set at 5 words. (The CVSD In FIFO interrupt will occur when there are 3 words left in the

FIFO, and the CVSD Out FIFO interrupt will occur when there are 3 or less empty words left in the FIFO.)

The limit is set to 5 words because Bluetooth audio data is transferred in packages of 10 bytes or

multiples of 10 bytes.

Because the PCM I/O interrupt requests can be handled by either the CPU or DSP interrupt controllers,

the interrupt requests are passed through the Audio Subsystem Controller (ASC), which is programmed to

route them to the interrupt controller. To use the PCM I/O interrupts, they must be enabled at three levels:

•

CVSD/PCM module—the interrupts must be enabled using the PCMINT bits in the CVCTRLn registers.

•

ASC module—the PCM I/O interrupts are assigned to ASC interrupt channels 5 (CVSD/PCM module

0) and 4 (CVSD/PCM module 1), so bits 5 and 4 in the ASCINTSEL register must be clear to select

the CPU interrupt controller or set to select the DSP interrupt controller.

•

Interrupt controller—the interrupt requests must be enabled in the interrupt controller. For the CPU

interrupt controller, these are interrupt requests IRQ25 (CVSD/ PCM module 0) and IRQ24

(CVSD/PCM module 1).

256

Dual CVSD/PCM Conversion Modules

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